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Carbon dioxide adsorption through carbon adsorbent structures: Effect of the porosity size, chemical potential and temperature

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COMPUTATIONAL MATERIALS SCIENCE 2018年 151卷 255-272页

作者： Kouetcha, Daniella Nguemalieu Ramezani, Hamidreza Mathieu-Cohaut, Nathalie Bhatia, Suresh K. Univ Orleans ICMN UMR CNRS 7374 Interfaces Confinement Mat & Nanostruct 1b Rue FerollerieCS 40059 F-45071 Orleans France Univ Orleans Ecole Polytech Interfaces Confinement Mat & Nanostruct ICMNUMR CNRS 7374 8 Rue Leonrad de Vinci F-45072 Orleans France Univ Queensland Sch Chem Engn St Lucia Qld 4072 Australia

In the present paper, the carbon dioxide molecule adsorption through nanoporous carbons has been studied at 248 [K], 298 [K] and 323 [K]. The 3-stage graphite, turbostratic carbon and activated carbon have been taken into account as nanoporous carbon structures with nearly the same simulation box size, i.e. 30 x 30 x 30 [angstrom]. The numerical experiments of the adsorption phenomenon of CO2 molecule have been successfully achieved by user-written massively parallel codes via MPI paradigm which has been carefully examined and evaluated including electrostatic charges, 3-site CO2 molecule and linear scalability issues for the parallel programming purposes. By taking advantage of the parallel programming and efficient algorithm paradigm, very accurate outcomes and highly portable implementations for High Performance Computing (HPC) have been obtained. The effect of nanoscale pore size and its distribution for the above-mentioned nanoporous carbons which are generated via user-written C+ + codes, have been studied by means of scalable parallel code. In the first stage, the carbon dioxide at bulk state has been investigated. Afterwards, the adsorption simulations have been achieved on regular and nearly regular nanoporous structures, i.e. 3-stage graphite including 6 [angstrom] and 12 [angstrom] interlayer distances (pore width), receptively. The activated carbon structure which is generated via Reverse Monte Carlo in Pikunic a al. (2003), has been considered for numerical experiments of adsorption as well. The comparison among these nanoporous carbons reveals a cross-over trend beyond a specific Adams constant value and this issue can be found out for the above-mentioned carbons as well as bulk case.

关键词： GCMC parallel programming Adsorption Nanoporous carbons Carbon dioxide Pore size Pore distribution

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MODEL OF SHELL METAL MOULD HEATING IN THE AUTOMOTIVE INDUSTRY

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APPLICATIONS OF MATHEMATICS 2018年第2期63卷 111-124页

作者： Mlynek, Jaroslav Knobloch, Roman Tech Univ Liberec Dept Math Studentska 2 Liberec 46117 Czech Republic

This article focuses on heat radiation intensity optimization on the surface of a shell metal mould. Such moulds are used in the automotive industry in the artificial leather production (the artificial leather is used, e.g., on car dashboards). The mould is heated by infrared heaters. After the required temperature is attained, the inner mould surface is sprinkled with special PVC powder. The powder melts and after cooling down it forms the artificial leather. A homogeneous temperature field of the mould is a necessary prerequisite for obtaining a uniform colour shade and material structure of the artificial leather. The article includes a description of a mathematical model that allows to calculate the heat radiation intensity on the outer mould surface for each fixed positioning of the infrared heaters. Next, we use this mathematical model to optimize the locations of the heaters to provide approximately the same heat radiation intensity on the whole outer mould surface during the heating process. The heat radiation intensity optimization is a complex task, because the cost function may have many local minima. Therefore, using gradient methods to solve this problem is not suitable. A differential evolution algorithm is applied during the optimization process. Asymptotic convergence of the algorithm is shown. The article contains a practical example including graphical outputs. The calculations were performed by means of Matlab code written by the authors.

关键词： heat radiation heat conduction optimization differential evolution algorithm mathematical model parallel programming

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MC64-Cluster: Many-Core CPU Cluster Architecture and Performance Analysis in B-Tree Searches

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COMPUTER JOURNAL 2018年第6期61卷 912-925页

作者： Jose Esteban, Francisco Diaz, David Hernandez, Pilar Antonio Caballero, Juan Dorado, Gabriel Galvez, Sergio Univ Cordoba Serv Informat Edificio Ramon y CajalCampus Rabanales E-14071 Cordoba Spain Univ Malaga ETSI Informat Dept Lenguajes & Ciencias Comp Campus Teatinos E-29071 Malaga Spain CSIC IAS Dept Agron Alameda Obispo S-N Cordoba 14080 Spain Univ Cordoba Dept Estadist Campus Rabanales C2-20N E-14071 Cordoba Spain Univ Cordoba Dept Bioquim & Biol Mol Campus Rabanales C6-1-E17 E-14071 Cordoba Spain

The MC64-Cluster computer platform was designed, based on many-core CPU microprocessors: Tile64. MC64-Cluster architecture was outlined in terms of both hardware and software, including commands available to manage jobs and provided application programming interfaces to communicate and synchronize tiles, making this system easy to use. Massively concurrent-searches of keys in B-trees, which are used in many applications, including bioinformatics, were used. Remarkable performance improvements were obtained when the cluster resources were combined with those available in host machine (hybrid or heterogeneous environments). These results were even more outstanding when analyzed in terms of performance-per-watt, highlighting their green-computing advantages. Together with the cluster architecture, they represent the main contributions of this work. To our knowledge, this is the first cluster implementation of this kind being developed.

关键词： parallel programming high-performance computing hardware architecture hybrid computing green computing bioinformatics B-tree

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An Efficient programming Skeleton for Clusters of Multi-Core Processors

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INTERNATIONAL JOURNAL OF parallel programming 2018年第6期46卷 1094-1109页

作者： Rad, Mina Hosseini Patooghy, Ahmad Fazeli, Mahdi Iran Univ Sci & Technol Dept Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

This paper proposes a divide and conquer skeleton which aids parallel system programmers by (1) reducing programming complexity, (2) shortening programming time, and (3) enhancing code efficiency. To do this, the proposed skeleton exploits three mechanisms of (1) work-stealing, and (2) communication/computation overlapping, and (3) architectural awareness in the proposed divide and conquer skeleton. Using the work-stealing mechanism, when a processing element reaches a low-load condition, the processing core fetches a new job from the waiting queue of other cores. The second mechanism uses special threads to enable the proposed skeleton to overlapping computations with communications. The third mechanism considers the architectural parameters of the host system e.g., size of L1 cache, network bandwidth, network latency to maximally match a divide and conquer problem with the proposed skeleton. To evaluate the proposed skeleton, three benchmarks of merge sort, fast Fourier transform, and standard matrix multiplication are developed by the proposed skeleton as well as customized programming. Experiments are done in both simulation and real implementation environments. The set of six codes are simulated using COTSon simulator and also implemented on 28 dual-core real system. Obtained results from simulations showed an average of 12.6% speed-up of the proposed skeleton as compared to the customized programming;obtained speed-up in real environment is 9.6%. Furthermore, programming aided by the proposed skeleton, is at least 70% faster than custom programming while this difference increases as the program volume increases.

关键词： Cluster computing Divide and conquer Multi-core processor parallel programming Skeleton

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A General Framework for Accelerating Swarm Intelligence Algorithms on FPGAs, GPUs and Multi-Core CPUs

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IEEE ACCESS 2018年 6卷 72327-72344页

作者： Li, Dalin Huang, Lan Wang, Kangping Pang, Wei Zhou, You Zhang, Rui Jilin Univ Coll Comp Sci & Technol Changchun 13002 Jilin Peoples R China Zhuhai Coll Jilin Univ Dept Comp Sci & Technol Zhuhai Lab Key Lab Symbol Computat & Knowledge En Minist Educ Zhuhai 519041 Peoples R China Univ Aberdeen Dept Comp Sci Aberdeen AB24 3UE Scotland

Swarm intelligence algorithms (SIAs) have demonstrated excellent performance when solving optimization problems including many real-world problems. However, because of their expensive computational cost for some complex problems, SIAs need to be accelerated effectively for better performance. This paper presents a high-performance general framework to accelerate SIAs (FASI). Different from the previous work which accelerates SIAs through enhancing the parallelization only, FASI considers both the memory architectures of hardware platforms and the dataflow of SIAs, and it reschedules the framework of SIAs as a converged dataflow to improve the memory access efficiency. FASI achieves higher acceleration ability by matching the algorithm framework to the hardware architectures. We also design deep optimized structures of the parallelization and convergence of FASI based on the characteristics of specific hardware platforms. We take the quantum behaved particle swarm optimization algorithm as a case to evaluate FASI. The results show that FASI improves the throughput of SIAs and provides better performance through optimizing the hardware implementations. In our experiments, FASI achieves a maximum of 290.7 Mb/s throughput which is higher than several existing systems, and FASI on FPGAs achieves a better speedup than that on GPUs and multi-core CPUs. FASI is up to 123 times and not less than 1.45 times faster in terms of optimization time on Xilinx Kintex Ultrascale xcku040 when compares to Intel Core i7-6700 CPU/ NVIDIA GTX1080 GPU. Finally, we compare the differences of deploying FASI on hardware platforms and provide some guidelines for promoting the acceleration performance according to the hardware architectures.

关键词： Field programmable gate arrays multicore processing parallel programming particle swarm optimization pipeline processing

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Partial differential equations preconditioner resilient to soft and hard faults

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2018年第5期32卷 658-673页

作者： Rizzi, F. Morris, K. Sargsyan, K. Mycek, P. Safta, C. Le Maitre, O. Knio, O. Debusschere, B. Sandia Natl Labs Scalable Modeling & Anal Systems Livermore CA USA Sandia Natl Labs Digital & Quantum Info Syst Dept Livermore CA USA Sandia Natl Labs POB 969MS9152 Livermore CA 94551 USA Duke Univ Durham NC 27706 USA Duke Univ Mech Engn & Mat Sci Durham NC 27706 USA

We present a domain-decomposition-based preconditioner for the solution of partial differential equations (PDEs) that is resilient to both soft and hard faults. The algorithm reformulates the PDE as a sampling problem, followed by a solution update through data manipulation that is resilient to both soft and hard faults. This reformulation allows us to recast the problem as a set of independent tasks, and exploit data locality to reduce global communication. We discuss two different parallel implementations: (a) a single program multiple data (SPMD) version based on a one-to-one mapping between subdomain and MPI processes responsible for both state and computation;and (b) an asynchronous server-client implementation where all state information is held by the servers and clients are designed solely as computational units. We present a scalability comparison of both implementations under nominal conditions, showing efficiency within similar to 80% for up to 12,000 cores. We present a resilience analysis under different fault scenarios based on the server-client implementation. This framework provides resiliency to hard faults such that if a client crashes, it stops asking for work, and the servers simply distribute the work among all of the other clients alive. Erroneous subdomain solves (e.g. due to soft faults) appear as corrupted data, which is either rejected if that causes a task to fail, or is seamlessly filtered out during the regression stage through a suitable noise model. Three different types of faults are modeled: hard faults modeling nodes (or clients) crashing;soft faults occurring during the communication of the tasks between server and clients;and soft faults occurring during task execution. We demonstrate the resiliency of the approach for a 2D elliptic PDE, and explore the effect of the faults at various failure rates.

关键词： Resilience scientific computing supercomputers parallel programming distributed computing client-server systems high-performance computing parallel algorithms software engineering fault tolerance message passing fault-tolerant systems partial differential equations

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Exploring manycore architectures for next-generation HPC systems through the MANGO approach

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MICROPROCESSORS AND MICROSYSTEMS 2018年第Sep.期61卷 154-170页

作者： Flich, Jose Agosta, Giovanni Ampletzer, Philipp Alonso, David Atienza Brandolese, Carlo Cappe, Etienne Cilardo, Alessandro Dragic, Leon Dray, Alexandre Duspara, Alen Fornaciari, William Fusella, Edoardo Gagliardi, Mirko Guillaume, Gerald Hofman, Daniel Hoornenborg, Ynse Iranfar, Arman Kovac, Mario Libutti, Simone Maitre, Bruno Martinez, Jose Maria Massari, Giuseppe Meinds, Koen Mlinaric, Hrvoje Papastefanakis, Ermis Picornell, Tomas Piljic, Igor Pupykina, Anna Reghenzani, Federico Staub, Isabelle Tornero, Rafael Zanella, Michele Zapater, Marina Zoni, Davide Univ Politecn Valencia Valencia Spain Politecn Milan DEIB Milan Italy PRO DESIGN Elect GmbH Bruckmuhl Germany Ecole Polytech Fed Lausanne ESL Lausanne Switzerland Ctr Reg Informat Commun Technol SCRL Benevento Italy Univ Zagreb Zagreb Croatia Eaton Ind SAS Montbonnot St Martin France Philips Med Syst Best Netherlands Thales Commun & Secur Gennevilliers France Univ Napoli Federico II Naples Italy

The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated.

关键词： High performance computing Heterogeneous architectures parallel programming programming model Resource management Power modeling Memory management Thermal management

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Incremental Banerjee test conditions committing for robust parallelization framework

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第5期26卷 2595-2604页

作者： Debbi, Aimad Eddine Bakhti, Haddi Ferhat Abbas Univ Fac Technol Dept Elect Setif Algeria Mohamed Boudhiaf Univ Fac Math & Informat Dept Comp Sci Msila Algeria

This paper describes the design of an automatic parallelization framework. The kernel supplied at its front end was suggested as an instrument for parallel potential assessment. It was used to measure the maximum achievable speedups in the major set of the CHStone benchmark suite programs. In such framework, we suggested the liberation of parallelism incrementally. We proposed a data dependency heuristic-based transformation method to make true dependences dissociation. We generated an internal representation (IR2), where the Banerjee test conditions are met. Two among three of Banerjee test conditions came to be committed. In shared memory many/multicore platforms, the third condition could be satisfied by privatization. We would be able to choose the safe and the opportune pairwise (mapping-privatization) scheme among a number of threads mapping scenarios that become available in the IR2 structure. Instrumentation on a subset of CHStone benchmark was carried out as a validity proof of our proposal, and the results confirmed that our framework kernel is robust.

关键词： Automatic parallelization parallel programming source-to-source compilation data dependency profiling parallelism assessment benchmarking

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Synergistic HW/SW Approximation Techniques for Ultralow-Power parallel Computing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2018年第5期37卷 982-995页

作者： Tagliavini, Giuseppe Rossi, Davide Marongiu, Andrea Benini, Luca Univ Bologna Dept Elect Elect & Informat Engn I-40136 Bologna Italy Swiss Fed Inst Technol Dept Informat Technol & Elect Engn CH-8092 Zurich Switzerland

Ultralow-power embedded systems have recently started the move to multicore designs. Aggressive voltage scaling techniques have the potential to reduce the power consumption within the admitted envelope, but memory operations on standard six-transistor static RAM (6T-SRAM) cells become unreliable at low voltages. While standard cell memory (SCM) overcomes this limitation, it has much lower area density than SRAM, and thus it is too costly. On the other hand, several applications have inherent tolerance to computation errors, and executing such workloads with approximation has already proven a viable way to reduce energy consumption. In this paper, we propose a novel HW/SW approach to design energy-efficient ultralow-power systems which combine the key ideas of approximate computing and hybrid memory systems featuring both SCM and 6T-SRAM. We introduce a novel hardware support to split error-tolerant data so to host most significant bits in the SCM and least significant bits (LSBs) in the 6T-SRAM. This allows to power the memory system at a low voltage while ensuring correct operation by binding possible (flip-bit) errors to the LSBs only. In addition, by organizing 6T-SRAM banks into multiple and independent voltage domains we enable fine-grained, software-controlled voltage switching policies. At the software level, we propose language constructs to specify what regions of code and what variables are tolerant to approximation, plus compiler support to optimize data placement. Experimental results show that our proposal can reduce the energy consumption of the memory system by 47% on average, always complying with the result accuracy required by practical applications constraints.

关键词： Approximation algorithms low-power electronics memory architecture multicore processing parallel programming

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Preparing the software engineer for a modern multi-core world

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2018年第Part1期118卷 247-263页

作者： Giacaman, Nasser Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Parallel & Reconfigurable Comp Grp Auckland New Zealand

parallel and Distributed Computing (PDC) was traditionally viewed as an advanced subject reserved for elective graduate courses. The last decade has seen two areas with rapid growth, whose synergy is demanding new skills for software engineers in a modem multi-core world. The first has been society's increasing demand for software engineering solutions, evident in the integral role that software plays in daily life. Unlike traditional PDC applications in the scientific and engineering domains, modem software applications are interacting directly with millions of users on mainstream laptops, smartphones and tablets. The second trend is that of multi-core processors powering such devices, which is further fueling the potential of software applications. This paper proposes a Modern parallel programming Framework that recognizes that successful software engineering in this domain involves a combination of hard skills and soft skills. A course dedicated to this goal is presented and evaluated, incorporating a research-infused, problem-based and active learning approach. (C) 2018 Elsevier Inc. All rights reserved.

关键词： Software engineering Concurrency parallel programming Active learning Research-infused learning Problem-based learning Soft skills Graphical user interfaces Object-oriented programming

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