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6th International Conference on Advanced Cloud and BigData (CBD)

作者： Cheng, Feng Yang, Zhe Soochow Univ Informat Proc Technol Prov Key Lab Comp Suzhou 215006 Jiangsu Peoples R China

ISBN: (纸本)9781538680346

Extracting minimal functional dependencies (MFDs) from relational databases is an import database analysis technique. With the advent of big data era, it is challenging to discover MFDs from big data, especially large-scale distributed data stored in many different sites. The key to discovering MFDs as fast as possible is pruning the useless candidate MFDs. And in most existed algorithms, it usually prunes candidate MFDs from top to bottom or from bottom to top. We present a new algorithms FastMFDs for discovering all MFDs from large-scale distributed data both from top to bottom and from bottom to top in parallel. We experimented our algorithm in real-life datasets, and our algorithm is more efficient and faster than the existed discovering algorithms.

关键词： Minimal Functional Dependency Big Data parallel programming

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Peachy parallel Assignments (EduHPC 2018)

Peachy Parallel Assignments (EduHPC 2018)

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IEEE/ACM Workshop on Education for High-Performance Computing (EduHPC)

作者： Ayguade, Eduard Alvarez, Lluc Banchelli, Fabio Burtscher, Martin Gonzalez-Escribano, Arturo Gutierrez, Julian Joiner, David A. Kaeli, David Previlon, Fritz Rodriguez-Gutiez, Eduardo Bunde, David P. Univ Politecn Cataluna Barcelona Supercomp Ctr Barcelona Spain Texas State Univ San Marcos TX USA Univ Valladolid Valladolid Spain Northeastern Univ Boston MA 02115 USA Kean Univ Union NJ USA Knox Coll Galesburg IL USA

ISBN: (纸本)9781728101903

Peachy parallel Assignments are a resource for instructors teaching parallel and distributed programming. These are high-quality assignments, previously tested in class, that are readily adoptable. This collection of assignments includes implementing a subset of OpenMP using pthreads, creating an animated fractal, image processing using histogram equalization, simulating a storm of high-energy particles, and solving the wave equation in a variety of settings. All of these come with sample assignment sheets and the necessary starter code.

关键词： parallel computing education High-Performance Computing education parallel programming OpenMP Pthreads CUDA Compiler and runtime systems Fractals Image processing Particle simulation Wave equation Peachy Assignments

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Thread-Local Concurrency: A Technique to Handle Data Race Detection at programming Model Abstraction 18

Thread-Local Concurrency: A Technique to Handle Data Race De...

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27th ACM International Symposium on High-Performance parallel and Distributed Computing (HPDC)

作者： Protze, Joachim Schulz, Martin Ahn, Dong H. Mueller, Matthias S. Rhein Westfal TH Aachen ITC Aachen Germany Tech Univ Munich Munich Germany LLNL Livermore CA USA

ISBN: (纸本)9781450357852

With greater adoption of various high-level parallel programming models to harness on-node parallelism, accurate data race detection has become more crucial than ever. However, existing tools have great difficulty spotting data races through these high-level models, as they primarily target low-level concurrent execution models (e.g., concurrency expressed at the level of POSIX threads). In this paper, we propose a novel technique to accurately detect those data races that can occur at higher levels of concurrent execution. The core idea of our technique is to introduce the general concept of Thread-Local Concurrency (TLC) as a new way to translate the concurrency expressed by a high-level programming paradigm into the lowexecution level understood by the existing tools. Specifically, we extend the definition of vector clocks to allow the existing state-of-the-art race detectors to recognize those races that occur at the higher level of concurrency with minor modifications to these tools. Our evaluation with our prototype implemented within ThreadSanitizer shows that TLC can allow the existing tool to detect these races accurately with only small additional analysis overheads.

关键词： parallel programming

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Towards Developing a Repository of Logical Errors Observed in parallel Code for Teaching Code Correctness

Towards Developing a Repository of Logical Errors Observed i...

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IEEE/ACM Workshop on Education for High-Performance Computing (EduHPC)

作者： Trung Nguyen Ba Arora, Ritu Univ Massachusetts Amherst MA 01003 USA Univ Texas Austin Texas Adv Comp Ctr Austin TX 78712 USA

ISBN: (纸本)9781728101903

Debugging parallel programs can be a challenging task, especially for the beginners. While the debuggers like DDT and TotalView can be extremely useful in tracking down the program statements that are connected to the bugs, often the onus is on the programmers to reason about the logic of the program statements in order to fix the bugs in them. These debuggers may neither be able to precisely indicate the logical errors in the parallel programs nor they may provide information on fixing those errors. Therefore, there is a need for developing tools and educational content on teaching the pitfalls in parallel programming and writing correct code. Such content can be useful to guide the beginners in avoiding commonly observed logical errors and in verifying the correctness of their parallel programs. In this paper, we 1) enumerate some of the logical errors that we have seen in the parallel programs (OpenMP, MPI, and CUDA) that were written by the beginners working with us, and 2) discuss the ways to fix those errors. The errors are mainly related to the data distribution, exiting distributed for-loops, and workload-imbalance. The documentation on these logical errors can contribute in enhancing the productivity of the beginners, and can potentially help them in their debugging efforts. We have added the code samples containing logical errors and their solutions in a Github repository so that the others in the community can reproduce the errors on their systems and learn from them. The content presented in this paper may also be useful for those developing high-level tools for detecting and removing logical errors in parallel programs.

关键词： logical errors parallel programming code correctness

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A Novel Actual Time Cyber Security Approach to Smart Grids 6

A Novel Actual Time Cyber Security Approach to Smart Grids

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6th International Istanbul Smart Grids and Cities Congress and Fair (ICSG)

作者： Buyuk, Oguzhan Oktay Camurcu, Ali Yilmaz Fatih Sultan Mehmet Vakif Univ Dept Comp Engn Istanbul Turkey

ISBN: (纸本)9781538644782

The purpose of this paper was to develop a novel actual time cyber security approach to smart grids. The developed way securely backed the smart meters among smart grids against external attacks in a distribution substation. Security is provided using Message Passing Interface (MPI). Newly configured Floyd-Warshall Algorithm was applied to MPI so as to represent a distribution of key pairs which was generated by Homomorphic Encryption. Simulation case studies were conducted on Raspberry Pi 2 Model B in order to illustrate how the mentioned approach can be built to execute the cyber security essentials via parallel programming techniques and Valgrind tools on a virtual distributed mechanism. Simulation results which use real world attack data demonstrated that the developed way is capable of accomplishing cyber security against outer attacks accurately, quickly and real time based sorting of the key pairs into each smart meter node in the demanded area.

关键词： Cyber Security Message Passing parallel programming Smart Grid Communication System Verification

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Theoretical and Practical Approaches for Teaching parallel Code Correctness

Theoretical and Practical Approaches for Teaching Parallel C...

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IEEE International Conference on High Performance Computing Workshops (HiPCW)

作者： Carlos Redondo Ritu Arora Trung Nguyen Ba The University of Texas at Austin Austin Texas USA Texas Advanced Computing Center The University of Texas at Austin Austin Texas USA University of Massachusetts at Amherst Amherst MA USA

ISBN: (数字)9781728148946

ISBN: (纸本)9781728148953

The introductory-level courses on parallel programming, typically, do not cover the topic of code correctness. Often, students learn about the logical errors in parallel programs and troubleshoot them through trial and error, and spend a significant amount of time and effort in the process. A systematic pedagogical approach to teaching parallel code correctness is therefore needed to enhance the productivity of students and instructors. In this paper, we describe some theoretical and practical approaches that can be adopted for assessing and teaching parallel code correctness. The theoretical approaches include using formal methods (e.g., Petri nets and Hoare Logic). We apply these approaches on the test cases discussed in this paper. The practical approach involves teaching code correctness through demonstrations. For enabling this, we have not only curated a repository of parallel programs with commonly made logical errors but have also added a high-level interface on top of the repository for quickly comparing fixed and incorrect versions of the sample code in the repository, seeing the explanation text on the errors, and searching the repository on the basis of the causes and symptoms of logical errors. The work presented in this paper can potentially motivate the instructors in including the content on code correctness in their parallel programming courses and trainings.

关键词： Petri nets Education Graphical user interfaces Databases parallel programming Mathematical model Graphics processing units

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Implementation of OpenMP Data-Sharing on CAPE 18

Implementation of OpenMP Data-Sharing on CAPE

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9th International Symposium on Information and Communication Technology (SoICT)

作者： Van Long Tran Renault, Eric Xuan Huyen Do Viet Hai Ha Univ Paris Saclay SAMOVAR Telecom SudParis CNRS Evry France Hue Ind Coll Hue Vietnam Hue Univ Coll Sci Hue Vietnam Hue Univ Coll Educ Hue Vietnam

ISBN: (纸本)9781450365390

CAPE (Checkpointing-Aided parallel Execution) is a framework that automatically translates and executes OpenMP on distributed memory architectures based on checkpoint technique. In some experiments, this approach shows high-performance on distributed memory system. However, it has not been fully developed yet. This paper presents an implementation of OpenMP data-sharing on CAPE that improves the capability, reduces checkpoint size and makes CAPE even more performance.

关键词： CAPE Checkpointing Aided parallel Execution OpenMP parallel programming Distributed Computing HPC

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Attached and Detached Closures in Actors 8

Attached and Detached Closures in Actors

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8th ACM SIGPLAN International Workshop on programming Based on Actors, Agents, and Decentralized Control (AGERE)

作者： Castegren, Elias Clarke, Dave Fernandez-Reyes, Kiko Wrigstad, Tobias Yang, Albert Mingkun KTH Royal Inst Technol Stockholm Sweden Uppsala Univ Informat Technol Uppsala Sweden Uppsala Univ Uppsala Sweden

ISBN: (纸本)9781450360661

Expressive actor models combine aspects of functional programming into the pure actor model enriched with futures. Such functional features include first-class closures which can be passed between actors and chained on futures. Combined with mutable objects, this opens the door to race conditions. In some situations, closures may not be evaluated by the actor that created them yet may access fields or objects owned by that actor. In other situations, closures may be safely fired off to run as a separate task. This paper discusses the problem of who can safely evaluate a closure to avoid race conditions, and presents the current solution to the problem adopted by the Encore language. The solution integrates with Encore's capability type system, which influences whether a closure is attached and must be evaluated by the creating actor, or whether it can be detached and evaluated independently of its creator. Encore's current solution to this problem is not final or optimal. We conclude by discussing a number of open problems related to dealing with closures in the actor model.

关键词： closures parallel programming concurrent programming type systems

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Emergency Landing Field Recognition Based on Elevation Data Using parallel Processing 37

Emergency Landing Field Recognition Based on Elevation Data ...

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IEEE/AIAA 37th Digital Avionics Systems Conference (DASC)

作者： Eckstein, Felix Wittich, Bjoern Schiffmann, Wolfram FernUniversitat Comp Architecture Grp Hagen Germany

ISBN: (纸本)9781538641125

In case of a forced emergency landing situation it is crucial to identify suitable landing fields rapidly and precisely. To safely land an aircraft, various options are possible. A premium choice would be a published airfield. But there are situations where such a location is unreachable - e.g. in regions with few widely scattered airfields or if the airplane's altitude is too low to reach a nearby airfield. In these cases, other flat terrains may be suitable to safely land the plane. If a satisfactory landing field is known, an Emergency Landing Assistant can be used to calculate an optimized route from the current position [3]. In this paper we present a parallel processing approach based on POSIX threads to identify suitable emergency landing fields. As input of the algorithm elevation data of a surface model is used. The landing fields are charaterized by a set of algorithm parameters which are based on different types of slope among the data points within a certain landing field. The recognized landing fields are scored according to their bumpiness measured by the variance of the altitude values and stored in a geo database for later usage in an emergency case.

关键词： emergency landing fields parallel programming threads elevation data

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A C-DAG task model for scheduling complex real-time tasks on heterogeneous platforms: Preemption matters

arXiv

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arXiv 2019年

作者： Zahaf, Houssam-Eddine Capodieci, Nicola Cavicchioli, Roberto Bertogna, Marko Lipari, Giuseppe

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time application for such architectures, the designer needs to make a number of difficult choices: On which processor should a certain task be implemented? Should a component be implemented in parallel or sequentially? These choices may have a great impact on feasibility, as the difference in the processor internal architectures impact on the tasks' execution time and preemption cost. To help the designer explore the wide space of design choices and tune the scheduling parameters, in this paper we propose a novel real-time application model, called C-DAG, specifically conceived for heterogeneous platforms. A C-DAG allows to specify alternative implementations of the same component of an application for different processing engines to be selected off-line, as well as conditional branches to model if-then-else statements to be selected at run-time. We also propose a schedulability analysis for the C-DAG model and a heuristic allocation algorithm so that all deadlines are respected. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We demonstrate the effectiveness of our approach on a large set of synthetic experiments by comparing with state of the art algorithms in the literature. Copyright © 2019, The Authors. All rights reserved.

关键词： parallel programming

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