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检索条件"主题词=Parallel programming"

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A parallelised distributed implementation of a Branch and Fix Coordination algorithm

A parallelised distributed implementation of a Branch and Fi...

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26th EURO-INFORMS Joint International Conference

作者： Pages-Bernaus, Adela Perez-Valdes, Gerardo Tomasgard, Asgeir Norwegian Univ Sci & Technol Inst Ind Econ & Technol Management Trondheim Norway SINTEF Technol & Soc Appl Econ Dept Trondheim Norway

Branch and Fix Coordination is an algorithm intended to solve large scale multi-stage stochastic mixed integer problems, based on the particular structure of such problems, so that they can be broken down into smaller subproblems. With this in mind, it is possible to use distributed computation techniques to solve the several subproblems in a parallel way, almost independently. To guarantee non-anticipativity in the global solution, the values of the integer variables in the subproblems are coordinated by a master thread. Scenario 'clusters' lend themselves particularly well to parallelisation, allowing us to solve some problems noticeably faster. Thanks to the decomposition into smaller subproblems, we can also attempt to solve otherwise intractable instances. In this work, we present details on the computational implementation of the Branch and Fix Coordination algorithm. (C) 2015 The Authors. Published by Elsevier B.V.

关键词： Stochastic mixed-integer problems Branch and fix coordination algorithm parallel programming

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Communication-aware parallelization Strategies for High Performance Applications

Communication-aware Parallelization Strategies for High Perf...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Ashraf, Imran Bertels, Koen Khammassi, Nader Le Lann, Jean-Christophe Delft Univ Technol Comp Engn Lab Delft Netherlands ENSTA Bretagne LabSTICC UMR CNRS 6285 Brest France

ISBN: (纸本)9781479987191

With the advent of multicore processor architectures and the existence of a huge legacy code base, the need for efficient and scalable parallelizing compilers is growing. Where multi-core processors were seen as the way forward to address the known challenges such as the memory, power and ILP wall, efficient parallelization to make use of the multiple cores, is still an open issue. In this paper, we present two complementary tools, MCROF and XPU which provide an alternative development path to parallelise applications and that address the challenges of identifying potential parallelism and exploiting it in a different way. The MCROF tool provides a detailed profile of the data flowing inside an application and the XPU programming paradigm provides an intuitive and simple interface to express parallelism as well as the necessary runtime support. We demonstrate through two different use cases that better performance up to 4x can be achieved than available commercial compilers.

关键词： Data-communication profiling program parallelization Multicore parallel programming

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CLTune: A Generic Auto-Tuner for OpenCL Kernels 9

CLTune: A Generic Auto-Tuner for OpenCL Kernels

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9th IEEE International Symposium on Embedded Multicore/Manycore Systems-on-Chip (MCSoC)

作者： Nugteren, Cedric Codreanu, Valeriu SURFsara HPC Ctr Amsterdam Netherlands

ISBN: (纸本)9781479986705

This work presents CLTune, an auto-tuner for OpenCL kernels. It evaluates and tunes kernel performance of a generic, user-defined search space of possible parameter-value combinations. Example parameters include the OpenCL workgroup size, vector data-types, tile sizes, and loop unrolling factors. CLTune can be used in the following scenarios: 1) when there are too many tunable parameters to explore manually, 2) when performance portability across OpenCL devices is desired, or 3) when the optimal parameters change based on input argument values (e.g. matrix dimensions). The auto-tuner is generic, easy to use, open-source, and supports multiple search strategies including simulated annealing and particle swarm optimisation. CLTune is evaluated on two GPU case-studies inspired by the recent successes in deep learning: 2D convolution and matrix-multiplication (GEMM). For 2D convolution, we demonstrate the need for auto-tuning by optimizing for different filter sizes, achieving performance on-par or better than the state-of-the-art. For matrix-multiplication, we use CLTune to explore a parameter space of more than two-hundred thousand configurations, we show the need for device-specific tuning, and outperform the clBLAS library on NVIDIA, AMD and Intel GPUs.

关键词： parallel programming public domain software software libraries 2D convolution CLTune GPU OpenCL kernels auto-tuner matrix-multiplication open-source Convolution Kernel Performance evaluation Search problems Simulated annealing Tuners Auto-Tuning GEMM OpenCL Convolution open source open source software Software libraries tabu search simulated annealing GRAPPER PICK UP Graphics Processing Unit Self tuning parallel programming Kernel Performance Evaluation Seeds Tuner Device Component

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Fast and Efficient parallel Computations Using a Cluster of Workstations to Simulate Flood Flows 4

Fast and Efficient Parallel Computations Using a Cluster of ...

引用

4th International Conference on Soft Computing, Intelligent System and Information Technology (ICSIIT)

作者： Mungkasi, Sudi Darmawan, J. B. Budi Sanata Dharma Univ Fac Sci & Technol Dept Math Tromol Pos 29 Yogyakarta 55002 Indonesia Sanata Dharma Univ Fac Sci & Technol Dept Informat Yogyakarta 55002 Indonesia

ISBN: (纸本)9783662467428;9783662467411

A strategy is proposed for fast and efficient parallel computations using a cluster of workstations to simulate flood flows. We implement ANUGA software to conduct flood simulations. ANUGA solves the two-dimensional shallow water equations using a finite volume method. ANUGA can be run in either sequential or parallel. We focus our work on parallel computations. Our computation scenarios are implemented on a cluster of workstations. parallel computation results are assessed based on execution time and efficiency. The strategy that we propose gives a significant advantage when we want to get fast and efficient computations using a cluster of workstations.

关键词： ANUGA software flood flow parallel programming

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Protocol-Based Verification of Message-Passing parallel Programs 2015

Protocol-Based Verification of Message-Passing Parallel Prog...

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ACM SIGPLAN International Conference on Object-Oriented programming, Systems, Languages, and Applications (OOPSLA)

作者： Lopez, Hugo A. Marques, Eduardo R. B. Martins, Francisco Ng, Nicholas Santos, Cesar Vasconcelos, Vasco Thudichum Yoshida, Nobuko Tech Univ Denmark Lyngby Denmark Univ Lisbon LaSIGE Fac Ciencias P-1699 Lisbon Portugal Univ London Imperial Coll Sci Technol & Med London England

ISBN: (纸本)9781450336895

We present ParTypes, a type-based methodology for the verification of Message Passing Interface (MPI) programs written in the C programming language. The aim is to statically verify programs against protocol specifications, enforcing properties such as fidelity and absence of deadlocks. We develop a protocol language based on a dependent type system for message-passing parallel programs, which includes various communication operators, such as point-to-point messages, broadcast, reduce, array scatter and gather. For the verification of a program against a given protocol, the protocol is first translated into a representation read by VCC, a software verifier for C. We successfully verified several MPI programs in a running time that is independent of the number of processes or other input parameters. This contrasts with alternative techniques, notably model checking and runtime verification, that suffer from the state-explosion problem or that otherwise depend on parameters to the program itself. We experimentally evaluated our approach against state-of-the-art tools for MPI to conclude that our approach offers a scalable solution.

关键词： Languages Verification Program verification parallel programming MPI Session types Dependent types

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A parallel Latent Semantic Indexing (LSI) Algorithm for Malay Hadith Translated Document Retrieval 1st

A Parallel Latent Semantic Indexing (LSI) Algorithm for Mala...

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1st International Conference on Soft Computing in Data Science (SCDS)

作者： Abd Rahman, Nurazzah Mabni, Zulaile Omar, Nasiroh Hanum, Haslizatul Fairuz Mohamed Rahim, Nik Nur Amirah Tuan Mohamad Univ Teknol MARA Fac Comp & Math Sci Shah Alam 40450 Malaysia

ISBN: (纸本)9789812879363;9789812879356

Latent Semantic Indexing (LSI) is one of the well-known searching techniques which match queries to documents in information retrieval applications. LSI has been proven to improve the retrieval performance, however, as the size of documents gets larger, current implementations are not fast enough to compute the result on a standard personal computer. In this paper, we proposed a new parallel LSI algorithm on standard personal computers with multicore processors to improve the performance of retrieving relevant documents. The proposed parallel LSI was designed to automatically run the matrix computation on LSI algorithms as parallel threads using multi-core processors. The Fork-Join technique is applied to execute the parallel programs. We used the Malay Translated Hadith of Shahih Bukhari from Jilid 1 until Jilid 4 as the test collections. The total number of documents used is 2028 of text files. The processing time during the pre-processing phase of the documents for the proposed parallel LSI is measured and compared to the sequential LSI algorithm. Our results show that processing time for pre-processing tasks using our proposed parallel LSI system is faster than sequential system. Thus, our proposed parallel LSI algorithm has improved the searching time as compared to sequential LSI algorithm.

关键词： Latent Semantic Indexing (LSI) parallel programming Fork-Join

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Green-CM: Energy efficient contention management for Transactional Memory 44

Green-CM: Energy efficient contention management for Transac...

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44th Annual International Conference on parallel Processing Workshops (ICPPW)

作者： Issa, Shady Romano, Paolo Brorsson, Mats Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781467375887

Transactional memory (TM) is emerging as an attractive synchronization mechanism for concurrent computing. In this work we aim at filling a relevant gap in the TM literature, by investigating the issue of energy efficiency for one crucial building block of TM systems: contention management. Green-CM, the solution proposed in this paper, is the first contention management scheme explicitly designed to jointly optimize both performance and energy consumption. To this end Green-TM combines three key mechanisms: i) it leverages on a novel asymmetric design, which combines different back-off policies in order to take advantage of dynamic frequency and voltage scaling;ii) it introduces an energy efficient design of the back-off mechanism, which combines spin-based and sleep-based implementations;iii) it makes extensive use of self-tuning mechanisms to pursue optimal efficiency across highly heterogeneous workloads. We evaluate Green-CM from both the energy and performance perspectives, and show that it can achieve enhanced efficiency by up to 2.35 times with respect to state of the art contention managers, with an average gain of more than 60% when using 64 threads.

关键词： Energy consumption Hardware Heuristic algorithms Instruction sets Memory management Spinning Time-frequency analysis Contention Management DVFS Energy Efficiency Transactional Memory Energy efficiency instruction sets Store management Heuristic algorithms Time frequency analysis energy consumption Spinning Computer hardware parallel programming Spin dynamic frequency thulium

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Improving the Reliability and the Performance of CAPE by Using MPI for Data Exchange on Network 1

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1st International Conference on Mobile, Secure, and Programmable Networking (MSPN)

作者： Van Long Tran Renault, Eric Viet Hai Ha Telecom SudParis Inst Mines Telecom Evry France Hue Univ Coll Educ Hue Vietnam

ISBN: (数字)9783319257440

ISBN: (纸本)9783319257440;9783319257433

CAPE - which stands for Checkpointing Aided parallel Execution - has demonstrated to be a high-performance and compliant OpenMP implementation for distributed memory systems. CAPE is based on the use of checkpoints to automatically distribute jobs of OpenMP parallel constructs to distant machines and to automatically collect the calculated results on these machines to the master machine. However, on the current version, the data exchange on networks use manual sockets that require time to establish connections between machines for each parallel construct. Furthermore, this technique is not really reliable due to the risk of conflicts on ports and the problem of data exchange using stream. This paper aims at presenting the impact of using MPI to improve the reliability and the performance of CAPE. Both socket and MPI implementations are analyzed and discussed, and performance evaluations are provided.

关键词： CAPE OpenMP MPI High-performance computing parallel programming

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parallelism Extraction in Embedded Software for Android Devices 15

Parallelism Extraction in Embedded Software for Android Devi...

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International Conference on Embedded Computer Systems Architectures Modeling and Simulation

作者： Aguilar, Miguel Angel Eusse, Juan Fernando Ray, Projjol Leupers, Rainer Ascheid, Gerd Sheng, Weihua Sharma, Prashant Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany Samsung R&D Inst Surrey England

ISBN: (纸本)9781467373111

In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor Systems on Chip (MPSoCs) is a widely accepted solution to provide a trade-off between these demands. However, programming MPSoCs is still a cumbersome task. Several research efforts have addressed this challenge in two complementary directions: paradigms for parallel programming and tools for parallelism extraction. However, most of these efforts are focused on the high performance domain and they do not consider the characteristics of the underlying platform. In this paper, we present an approach to extract multiple forms of parallelism from sequential C code, which is applied to widespread Android mobile devices. We show the effectiveness of our work by parallelizing relevant embedded benchmarks on a quad-core Nexus 7 tablet.

关键词： Androids Embedded software parallelism Synclitism Methyltestosterone Embedded device Multiple forms parallel programming everyday life C CODES

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Compiler Assisted Load Balancing on Large Clusters 24

Compiler Assisted Load Balancing on Large Clusters

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24th International Conference on parallel Architecture and Compilation (PACT)

作者： Deodhar, Vinit Parikh, Hrushit Gavrilovska, Ada Pande, Santosh Georgia Inst Technol Coll Comp Atlanta GA 30332 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9781467395243

Load balancing of tasks across processing nodes is critical for achieving speed up on large scale clusters. Load balancing schemes typically detect the imbalance and then migrate the load from an overloaded processing node to an idle or lightly loaded processing node and thus, estimation of load critically affects the performance of load balancing schemes. On large scale clusters, the latency of load migration between processing nodes (and the energy) is also a significant overhead and any missteps in load estimation can cause significant migrations and performance losses. Currently, the load estimation is done either by profile or feedback driven approaches in sophisticated systems such as Charm++, but such approaches must be re-thought in light of some workloads such as Adaptive Mesh Refinement (AMR) and multiscale physics where the load variations could be quite dynamic and rapid. In this work we propose a compiler based framework which performs precise prediction of the forthcoming workload. The compiler driven load prediction technique performs static analysis of a task and derives an expression to predict load of a task and hoists it as early as possible in the control flow of execution. The compiler also inserts corrector expressions at strategic program points which refine the reachability probability of the load as well as its estimation. The predictor and the corrector expressions are evaluated at runtime and the predicted load information is refined as the execution proceeds and is eventually used by load balancer to take efficient migration decisions. We present an implementation of the above in the Rose compiler and the Charm++ parallel programming framework. We demonstrate the effectiveness of the framework on some key benchmarks that exhibit dynamic variations and show how the compiler framework assists load balancing schemes in Charm++ to provide significant gains.

关键词： Distributed computing Processor scheduling parallel programming Petascale Computing

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