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International Conference on High Performance Computing

作者： Ben Michalowicz Kaushik Kandadi Suresh Hari Subramoni Mustafa Abduljabbar Dhabaleswar K. Panda Steve Poole Department of Computer Science and Engineering The Ohio State University Columbus USA Los Alamos National Laboratory

ISBN: (数字)9798331509095

ISBN: (纸本)9798331509101

One-sided communication is one of many approaches to use for data transfer in High-Performance Computing (HPC) applications. One-sided operations require less demand on parallel programming libraries and do not require HPC hardware to issue acknowledgments of successful data transfer. Thanks to its inherently non-blocking nature, one-sided communication is also useful for improving overlap between communication and compute. As with any non-blocking communication, however, we run into the issue of message progression getting interleaved with computation. With the advent of Smart Network Cards (SmartNIC) such as NVIDIA's BlueField Data Processing Units (DPU), we can offload the communication and message progression to these devices to improve the overlap of communication and compute. In this paper, we propose designs for efficient offloading of one-sided communication. We show how our designs can be used for offloading both MPI one-sided “put” and “get” and OpenSHMEM's non-blocking “put” and “get”. Using a Block Sparse Matrix-Multiplication Kernel (BSPMM), we show that our designs achieve over 96% improvement in runtime over pure-host execution for communication offload. We also briefly explore initial compute offload ideas for such one-sided kernels and show over 91% improvement in runtime here.

关键词： Runtime parallel programming High performance computing Memory management Data transfer Libraries Hardware Sparse matrices Kernel

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UNR: Unified Notifiable RMA Library for HPC

arXiv

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arXiv 2024年

作者： Feng, Guangnan Xie, Jiabin Dong, Dezun Lu, Yutong Sun Yat-sen University Guangzhou China Changsha China

Remote Memory Access (RMA) enables direct access to remote memory to achieve high performance for HPC applications. However, most modern parallel programming models lack schemes for the remote process to detect the completion of RMA operations. Many previous works have proposed programming models and extensions to notify the communication peer, but they did not solve the multi-NIC aggregation, portability, hardware-software co-design, and usability problems. In this work, we proposed a Unified Notifiable RMA (UNR) library for HPC to address these challenges. In addition, we demonstrate the best practice of utilizing UNR within a real-world scientific application, PowerLLEL. We deployed UNR across four HPC systems, each with a different interconnect. The results show that PowerLLEL powered by UNR achieves up to a 36% acceleration on 1728 nodes of the Tianhe-Xingyi supercomputing system. Copyright © 2024, The Authors. All rights reserved.

关键词： parallel programming

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Efficient Multicore Computing and High-Precision Arithmetic: A Comprehensive Guide to Multicore and Big Number programming

Efficient Multicore Computing and High-Precision Arithmetic:...

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International Conference on Communication Systems and Network Technologies (CSNT)

作者： Taniya Hasija K. R. Ramkumar Amanpreet Kaur Sudesh Kumar Mittal Bhupendra Singh Chitkara University Institute of Engineering and Technology Chitkara University Punjab India Centre for Artificial Intelligence & Robotics Defence Research and Development Organization Bangalore India

ISBN: (数字)9798350305463

ISBN: (纸本)9798350305470

Today system and application programming is moving toward concurrent and parallel programming with the development of multicore and multiprogramming architectures. In an effort to improve study performance, researchers are looking for more efficient methods to include multiprocessing and multicore programming into their simulation systems. This article provides an overview of multicore programming and illustrates how it can be implemented. The paper also focusing the limitations of primitive data types for diverse applications, especially in the context of computer systems. The article delves into the necessity of big numbers and arithmetic on a significant scale. Focusing on C programming, the article showcases the implementation of big numbers, providing scholars with a comprehensive understanding of the concept and its practical realization.

关键词： Knowledge engineering Codes Multicore processing parallel programming Communication systems Focusing Computer architecture

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Analysis of Different Algorithmic Design Techniques for Seam Carving

arXiv

引用

arXiv 2024年

作者： Ali, S. Muhammad Aijaz, Owais Uyghur, Yousuf Habib University Karachi Pakistan

Seam carving, a content-aware image resizing technique, has garnered significant attention for its ability to resize images while preserving important content. In this paper, we conduct a comprehensive analysis of four algorithmic design techniques for seam carving: brute-force, greedy, dynamic programming, and GPU-based parallel algorithms. We begin by presenting a theoretical overview of each technique, discussing their underlying principles and computational complexities. Subsequently, we delve into empirical evaluations, comparing the performance of these algorithms in terms of runtime efficiency. Our experimental results provide insights into the theoretical complexities of the design techniques. © 2024, CC BY.

关键词： parallel programming

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Adaptive Prefetching for Fine-grain Communication in PGAS Programs

Adaptive Prefetching for Fine-grain Communication in PGAS Pr...

引用

International Symposium on parallel and Distributed Processing (IPDPS)

作者： Thomas B. Rolinger Alan Sussman NVIDIA Austin TX USA University of Maryland College Park MD USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Applications that require distributed-memory systems and exhibit irregular memory access patterns present both productivity and performance challenges. This is largely due to the fine-grain communication that arises from irregular memory accesses to distributed data. The Partitioned Global Address Space (PGAS) model provides a globally shared address space and one-sided communication, making it well suited for implementing irregular codes. However, while the PGAS model provides productivity advantages, irregular applications have difficulty achieving high performance due to the cost of fine-grain remote accesses. One way to improve the performance of such PGAS programs is to prefetch remote data before it is needed, thereby hiding communication latency. The challenges of applying prefetching are computing the prefetch distance (i.e., how far ahead to issue prefetches), determining when prefetching will be profitable, and modifying the program to perform prefetching. In this work, we present an adaptive prefetching optimization that can be applied to PGAS programs with irregular memory access patterns. We target the Chapel parallel programming language, which implements a PGAS model. Our optimization leverages runtime information to adjust the prefetch distance and to pause/resume prefetching when that is likely to provide performance gains. Furthermore, we develop compiler support to automatically apply the optimization without requiring user intervention. We evaluate the optimization across five different distributed-memory systems and four workloads. We observe runtime speed-ups of 0.5 – 377x for the Chapel workloads when compared to not prefetching, and 3 – 215x when compared to implementations written in UPC, OpenSHMEM, and one-sided MPI.

关键词： Productivity Distributed processing Runtime parallel programming Prefetching Memory management Distributed databases

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Towards Accelerating k-NN with MPI and Near-Memory Processing

Towards Accelerating k-NN with MPI and Near-Memory Processin...

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IEEE International Symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Hooyoung Ahn Seonyoung Kim Yoomi Park Woojong Han Nick Contini Bharath Ramesh Mustafa Abduljabbar Dhabaleswar K. Panda Supercomputing Technology Research Center Electronics and Telecommunications Research Institute Department of Computer Science and Engineering The Ohio State University

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Message Passing Interface (MPI) is a common parallel programming model in High-Performance Computing fields. Recently, it has been widely used in Artificial Intelligence (AI) applications. However, the performance of those applications is limited by the memory wall problem, which is the performance gap between the processor and memory. To address these problems, we propose a novel computing architecture for accelerating k-NN query, which is the key operation of AI applications. The proposed computing architecture involves two or more computing nodes within a rack using the memory of an NMP device as a communication buffer and the accelerator of the NMP device for MPI collective communication. The superiority of the proposed method is that it reduces data copying during local computation and eliminates the network cost of gathering local computation results for global computation. Furthermore, it can enhance performance by processing data in the device's memory through near-memory processing. However, since these NMP devices are still in development, with no commercially available products currently, we have undertaken the task of developing them ourselves. Despite these circumstances, to demonstrate the feasibility of our proposed approach, we have implemented it in a single-node environment without making any unreasonable assumptions and have compared it with conventional approaches. Although we are using a single-node environment, we have designed a more sophisticated architecture, analyzed the time complexity, and compared the estimated performance of both the conventional and proposed approaches. We can conclude that the proposed computing architecture is feasible, and we anticipate an even more performance enhancement in a multi-node environment.

关键词： Performance evaluation Costs parallel programming Message passing High performance computing Conferences Computer architecture

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UniFaaS: programming across Distributed Cyberinfrastructure with Federated Function Serving

UniFaaS: Programming across Distributed Cyberinfrastructure ...

引用

International Symposium on parallel and Distributed Processing (IPDPS)

作者： Yifei Li Ryan Chard Yadu Babuji Kyle Chard Ian Foster Zhuozhao Li Dept. of Computer Science and Engineering Southern University of Science and Technology Shenzhen China Data Science and Learning Division Argonne National Laboratory Lemont IL USA Dept. of Computer Science University of Chicago Chicago IL USA

ISBN: (数字)9798350387117

ISBN: (纸本)9798350387124

Modern scientific applications are increasingly decomposable into individual functions that may be deployed across distributed and diverse cyberinfrastructure such as supercomputers, clouds, and accelerators. Such applications call for new approaches to programming, distributed execution, and function-level management. We present UniFaaS, a parallel programming framework that relies on a federated function-as-a-service (FaaS) model to enable composition of distributed, scalable, and high-performance scientific workflows, and to support fine-grained function-level management. UniFaaS provides a unified programming interface to compose dynamic task graphs with transparent wide-area data management. UniFaaS exploits an observe-predict-decide approach to efficiently map workflow tasks to target heterogeneous and dynamic resources. We propose a dynamic heterogeneity-aware scheduling algorithm that employs a delay mechanism and a re-scheduling mechanism to accommodate dynamic resource capacity. Our experiments show that UniFaaS can efficiently execute workflows across computing resources with minimal scheduling overhead. We show that UniFaaS can improve the performance of a real-world drug screening workflow by as much as 22.99% when employing an additional 19.48% of resources and a montage workflow by 54.41% when employing an additional 47.83% of resources across multiple distributed clusters, in contrast to using a single cluster.

关键词： Scheduling algorithms parallel programming Heuristic algorithms parallel processing Elasticity Dynamic scheduling Supercomputers

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Computation Augmentation Techniques for Computing Continuum

Computation Augmentation Techniques for Computing Continuum

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Cluster, Cloud and Internet Computing Workshops (CCGridW), IEEE/ACM International Symposium on

作者： George-Mircea Grosu Silvia-Elena Nistor Radu-Ioan Ciobanu Joanna Kolodziej Florin Pop National University of Science and Technology Politehnica Bucharest Romania NASK Warsaw and Cracow University of Technology Poland Department of Computer Sciences Cracow University of Technology Cracow Poland National Institute for Research and Development in Informatics (ICI) Bucharest Romania Academy of Romanian Scientists Bucharest Romania

ISBN: (数字)9798350377514

ISBN: (纸本)9798350377521

We are witnessing a tremendous expansion in computational power, leading to monumental technological advances with various practical applications. The need for parallelism originated from the limitations of single-processing performance. Increasing the transistor density on integrated circuits was the way to go, thus creating faster and more complex monolithic processors. However, these circuits approached their limits of hardware expansion, so the single-processor model has become unreliable and insufficient overall. This is how multicore architectures were born and, with them, the notion of parallel computing. Our research background in the Drop Computing paradigm and Interest in studying parallel programming paradigms encouraged us to propose a new approach towards parallel processing in mobile, ad-hoc, opportunistic networks. This paper adapts one fundamental message-passing standard for parallel architectures within the Drop Computing context. We define a new library DroMPI. Besides the challenges of parallel programming, the solution has to address the challenges imposed by hardware constraints, limited resources, and the decentralized model specific to Drop Computing.

关键词： Program processors parallel programming Multicore processing Computational modeling parallel processing Hardware Libraries Transistors Integrated circuit modeling Standards

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High-level Stream Processing: A Complementary Analysis of Fault Recovery

arXiv

引用

arXiv 2024年

作者： Vogel, Adriano Henning, Sören Perez-Wohlfeil, Esteban Ertl, Otmar Rabiser, Rick JKU Dynatrace Co-Innovation Lab LIT CPS Lab Johannes Kepler University Linz Linz Austria Dynatrace Research Linz Austria LIT CPS Lab Johannes Kepler University Linz Linz Austria

parallel computing is very important to accelerate the performance of software systems. Additionally, considering that a recurring challenge is to process high data volumes continuously, stream processing emerged as a paradigm and software architectural style. Several software systems rely on stream processing to deliver scalable performance, whereas open-source frameworks provide coding abstraction and high-level parallel computing. Although stream processing's performance is being extensively studied, the measurement of fault tolerance-a key abstraction offered by stream processing frameworks-has still not been adequately measured with comprehensive testbeds. In this work, we extend the previous fault recovery measurements with an exploratory analysis of the configuration space, additional experimental measurements, and analysis of improvement opportunities. We focus on robust deployment setups inspired by requirements for near real-time analytics of a large cloud observability platform. The results indicate significant potential for improving fault recovery and performance. However, these improvements entail grappling with configuration complexities, particularly in identifying and selecting the configurations to be fine-tuned and determining the appropriate values for them. Therefore, new abstractions for transparent configuration tuning are also needed for large-scale industry setups. We believe that more software engineering efforts are needed to provide insights into potential abstractions and how to achieve them. The stream processing community and industry practitioners could also benefit from more interactions with the high-level parallel programming community, whose expertise and insights on making parallel programming more productive and efficient could be extended. Copyright © 2024, The Authors. All rights reserved.

关键词： parallel programming

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Taskgrind: Heavyweight Dynamic Binary Instrumentation for parallel Programs Analysis

Taskgrind: Heavyweight Dynamic Binary Instrumentation for Pa...

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High Performance Computing, Networking, Storage and Analysis, SC-W: Workshops of the International Conference for

作者： Romain Pereira George Stelle Patrick Carribault Avalon LIP ENS Inria Lyon France Los Alamos National Laboratory Los Alamos New Mexico United States CEA DAM DIFF-91297 Arpajon Université Paris-Saclay CEA Laboratoire en Informatique Haute Performance pour le Calcul et la Simulation Bruyères-le-Châtel France

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Determinacy races are concurrent programming hazards occurring when two accesses on the same memory address are not ordered, and at least one is writing. Their presence hints at a correctness error, particularly under asynchronous task-based parallel programming models. This paper introduces Taskgrind: a Valgrind tool for memory access analysis of parallel programming models such as Cilk or OpenMP. We illustrate the tool’s capabilities with a determinacy-race analysis and confront it with state-of-the-art tools. Results show fewer false negatives and memory overheads on a set of microbenchmarks and LULESH, with meaningful error reports toward assisting programmers when parallelizing programs.

关键词： Concurrent computing Analytical models parallel programming Instruments High performance computing Conferences Writing Hazards Performance analysis

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