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检索条件"主题词=Parallel programming"

共 6686 条记录，以下是931-940 订阅

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PaScal Viewer: A Tool for the Visualization of parallel Scalability Trends 6th

PaScal Viewer: A Tool for the Visualization of Parallel Scal...

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5th International Workshop on Visual Performance Analysis (VPA)

作者： da Silva, Anderson B. N. Cunha, Daniel A. M. Silva, Vitor R. G. Furtunato, Alex F. de A. Xavier-de-Souza, Samuel IFPB Pesquisa Inovacao & Posgrad Joao Pessoa Paraiba Brazil Univ Fed Rio Grande do Norte Dept Engn Comp & Automacao Natal RN Brazil IFRN Tecnol Informacao Natal RN Brazil

ISBN: (纸本)9783030178727;9783030178710

Taking advantage of the growing number of cores in super-computers to increase the scalability of parallel programs is an increasing challenge. Many advanced profiling tools have been developed to assist programmers in the process of analyzing data related to the execution of their program. Programmers can act upon the information generated by these data and make their programs reach higher performance levels. However, the information provided by profiling tools is generally designed to optimize the program for a specific execution environment, with a target number of cores and a target problem size. A code optimization driven towards scalability rather than specific performance requires the analysis of many distinct execution environments instead of details about a single environment. With the goal of providing more useful information for the analysis and optimization of code for parallel scalability, this work introduces the PaScal Viewer tool. It presents an novel and productive way to visualize scalability trends of parallel programs. It consists of four diagrams that offers visual support to identify parallel efficiency trends of the whole program, or parts of it, when running on scaling parallel environments with scaling problem sizes.

关键词： parallel programming Efficiency Scalability Performance optimization Visualization tool

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PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference 13

PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Cam...

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13th International Conference on Distributed Smart Cameras (ICDSC)

作者： Carballo-Hernandez, Walther Berry, Francois Pelcat, Maxime Arias-Estrada, Miguel Inst Pascal Dept Images Percept Syst & Robot Aubiere France UMR CNRS Inst Natl Sci Appliquees INSA Rennes IETR Dept Images Rennes France INAOE Dept Comp Sci Puebla Mexico

ISBN: (纸本)9781450371896

The success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. This task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, Processing Element (PE) and communication. This article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. The built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. The selected heterogeneous platform embeds an Nvidia (R) Jetson TX2 for the CPU-GPU side and an Intel Altera (R) Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. This test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Heterogeneous Computing Edge Computing Internet of Things parallel programming Single Instruction Multiple Data Pipelining Models of Computation and Architecture

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Multilevel Checkpoint/Restart for Large Computational Jobs on Distributed Computing Resources 38

Multilevel Checkpoint/Restart for Large Computational Jobs o...

引用

IEEE 38th International Symposium on Reliable Distributed Systems (SRDS)

作者： Gholami, Masoud Schintke, Florian Zuse Inst Berlin Berlin Germany

ISBN: (纸本)9781728142227

New generations of high-performance computing applications depend on an increasing number of components to satisfy their growing demand for computation. On such large systems, the execution of long-running jobs is more likely affected by component failures. Failure classes vary from frequent transient memory faults to rather rare correlated node errors. Multilevel checkpoint/restart has been introduced to proactively cope with failures at different levels. Writing checkpoints on slower stable devices, which survive fatal failures, causes more overhead than writing them on fast devices (main memory or local SSD), which, however, only protect against light faults. Given a graph of the components of a particular storage hierarchy mapping their fault-domains and their expected mean time to failure (MTTF), we optimize the checkpoint frequencies for each level of the storage hierarchy (multilevel checkpointing) to minimize the overhead and runtime of a given job. We reduce the checkpoint/restart overhead of large dataintensive jobs compared to state-of-the-art solutions on multilevel checkpointing by up to 10 percent in the investigated cases. The improvement increases further with growing checkpoint sizes.

关键词： Checkpoint Checkpoint/restart Checkpointing Distributed computing Exascale Fault tolerance High performance computing Hpc Large jobs Mpi Mttf Multilevel checkpoint restart Multilevel checkpoint/restart parallel programming Supercomputer

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Multi-accelerator extension in OpenMP based on PGAS model 2019

Multi-accelerator extension in OpenMP based on PGAS model

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International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia)

作者： Nakao, Masahiro Murai, Hitoshi Sato, Mitsuhisa RIKEN Ctr Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781450366328

Many systems used in HPC field have multiple accelerators on a single compute node. However, programming for multiple accelerators is more difficult than that for a single accelerator. Therefore, in this paper, we propose an OpenMP extension that allows easy programming for multiple accelerators. We extend existing OpenMP syntax to create Partitioned GlobalAddress Space (PGAS) on separated memories of several accelerators. The feature enables users to perform programming to use multiple accelerators in ease. In performance evaluation, we implement the STREAM Triad and the HIMENO benchmarks using the proposed OpenMP extension. As a result of evaluating the performance on a compute node equipped with up to four GPUs,we con firm that the proposed OpenMP extension demonstrates sufficient performance.

关键词： OpenMP accelerator partitioned global address space parallel programming

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Executable Modelling for Highly parallel Accelerators 22

Executable Modelling for Highly Parallel Accelerators

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ACM/IEEE 22nd International Conference on Model Driven Engineering Languages and Systems Companion (MODELS-C)

作者： Addazi, Lorenzo Ciccozzi, Federico Lisper, Bjorn Malardalen Univ Sch Innovat Design & Engn Vasteras Sweden

ISBN: (纸本)9781728151250

High-performance embedded computing is developing rapidly since applications in most domains require a large and increasing amount of computing power. On the hardware side, this requirement is met by the introduction of heterogeneous systems, with highly parallel accelerators that are designed to take care of the computation-heavy parts of an application. There is today a plethora of accelerator architectures, including GPUs, many-cores, FPGAs, and domain-specific architectures such as AI accelerators. They all have their own programming models, which are typically complex, low-level, and involve explicit parallelism. This yields error-prone software that puts the functional safety at risk, unacceptable for safety-critical embedded applications. In this position paper we argue that high-level executable modelling languages tailored for parallel computing can help in the software design for high performance embedded applications. In particular, we consider the data-parallel model to be a suitable candidate, since it allows very abstract parallel algorithm specifications free from race conditions. Moreover, we promote the Action Language for fUML (and thereby fUML) as suitable host language.

关键词： parallel programming fUML Alf UML modelling languages high-performance computing data-parallelism executable models

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Case Study: Using Project Based Learning to Develop parallel Programing and Soft Skills 33

Case Study: Using Project Based Learning to Develop Parallel...

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33rd IEEE International parallel and Distributed Processing Symposium (IPDPS)

作者： Younis, Awad A. Sunderraman, Rajshekhar Metzler, Mike Bourgeois, Anu G. Georgia State Univ Atlanta GA 30303 USA

ISBN: (纸本)9781538655559

In today's environment, where every computer, including cell phones, are multicore, it is essential that students develop parallel programming skills. It remains a challenge to develop effective techniques for teaching parallel programing skills. Another challenge is finding time within already packed lectures to cover additional material. To that end, we investigate the effectiveness of using Project Based Learning (PBL) to teach parallel programming skills early in the curriculum by developing and incorporating a PBL module into CSc 3210 (Computer Organization and programming). This is a core course taken by all computer science majors and is a prerequisite to many of our senior-level classes. In our case study, 124 students are organized into 26 diverse groups, with four or five students per group, and assigned five project assignments, each of two-weeks duration. Given a Raspberry PI, students will explore its multicore architecture and create programs for shared memory parallelism using OpenMP and C language. Our results show that incorporating this PBL module has a significant and direct effect on the student's growth in parallel programming skills. As a side benefit, we also show that there is a direct improvement on a student's personal growth in terms soft skills, which is essential in the professional development and success in the workplace. By having students experience PBL in an early class, close to the midpoint of the academic program, it can serve as a mini-capstone project. Furthermore, students can collaboratively learn by themselves (through teamwork) and apply the fundamentals of parallel programming skills without the need for separate lectures, labs, or workshops.

关键词： parallel Computing parallel programming OpenMP Shared Memory Project Based Learning Raspberry PI Soft Skills Teamwork Technology

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MPI Scaling Up for Powerlist Based parallel Programs 27

MPI Scaling Up for Powerlist Based Parallel Programs

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27th Euromicro International Conference on parallel, Distributed and Network-Based Processing (PDP)

作者： Niculescu, Virginia Bufnea, Darius Sterca, Adrian Babes Bolyai Univ Fac Math & Comp Sci Cluj Napoca Romania

ISBN: (纸本)9781728116440

Powerlists are recursive data structures that together with their associated algebraic theories could offer both a methodology to design parallel algorithms and parallel programming abstractions to ease the development of parallel applications This has been also proved by a concrete development of such a framework that allows easy, efficient, and reliable implementation of Java parallel programs on shared memory systems. The paper presents a highly scalable version of this framework by extending it to distributed memory systems based on an MPI implementation. Through this extension we may use the framework to develop Java parallel programs also on distributed memory systems such as clusters. The design of the framework enables flexibility in defining the appropriate execution type depending on the execution system and its characteristics. Therefore, it is possible to choose MPI execution (ithat also could be combined with multithreading) if the available system includes an MPI platform, or simple multithreading execution. Examples are given and performance experiments are conducted. The performance analysis of these applications emphasises the utility and the efficiency of this framework extension.

关键词： parallel programming scaling recursive structures Java MPI performance models

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Using the AlgoWiki Open Encyclopedia of parallel Algorithmic Features in HPC Education 13th

Using the AlgoWiki Open Encyclopedia of Parallel Algorithmic...

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13th International Scientific Conference on parallel Computational Technologies (PCT)

作者： Antonov, Alexander Voevodin, Vladimir Lomonosov Moscow State Univ Moscow Russia

ISBN: (纸本)9783030281632;9783030281625

AlgoWiki is an open encyclopedia of algorithm properties and their implementations on various hardware and software platforms. It can be used for various purposes, such as finding the optimal algorithm for addressing a particular problem, analyzing the information structure of an application, or comparing the efficiency of different implementations of the same algorithm. In this article, we consider several options for using AlgoWiki to illustrate various concepts and notions in the Body of Knowledge and Skills for parallel computation and supercomputer technologies. The approbation of these options is conducted as part of the courses "Supercomputers and parallel Data Processing" and "Super-computer Simulation and Technologies", taught in the Computational Mathematics and Cybernetics Department at Lomonosov Moscow State University.

关键词： AlgoWiki High-performance computing education Structure of parallel algorithms Information structure parallelism resource parallel programming Supercomputers

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parallel Simulation of Digital Logic Circuits Using Message Passing via CSP as an Educational Tool 5th

Parallel Simulation of Digital Logic Circuits Using Message ...

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5th Ibero-American Workshop on Human-Computer Interaction (HCI-Collab)

作者： Rossainz-Lopez, Mario Ceron-Garnica, Carmen Archundia-Sierra, Etelvina Cervantes-Marquez, Patricia Carrasco-Limon, David Sanchez-Rinza, Barbara Benemerita Univ Autonoma Puebla Ave San Claudio & 14 Sur Puebla 72000 Pue Mexico

ISBN: (纸本)9783030373856;9783030373863

The present work shows an educational application of practical utility for the learning of the parallel and Concurrent programming with passage of messages, through the simulation of the digital logical circuits, as an excellent example of the inherent parallelism in the behavior of this type of systems. The Java class library called JPMI is used, which provides the base classes to generate processes, channels and composition of processes: sequential, parallel and alternative;for the parallel implementation of the most useful gates in the area of digital systems such as, the AND, OR and NOT gates. It shows a basic case study of the use of the JPMI library for the parallel implementation of a simple digital logic circuit and with this implementation simulate its logical behavior. But the full implementation of a 4-bit digital logic counter as an educational application or simulator is also shown. The objective of this work is, on the one hand, to demonstrate that the proposed implementations help the student through the simulation to understand and learn both the construction and the functioning of the digital systems, and on the other hand to show the inherent relationship of the parallelism with the operation of these systems.

关键词： Digital logic circuit Digital systems Logic gates JPMI CSP Educational simulation parallel programming Message passing

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Improve Student Performance Using Moderated Two-Stage Projects 19

Improve Student Performance Using Moderated Two-Stage Projec...

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4th ACM Conference on Global Computing Education (CompEd)

作者： Chen, Juan Cao, Yingjun Du, Linlin Ouyang, Youwen Shen, Li Natl Univ Def Technol Coll Comp Changsha Hunan Peoples R China Univ Calif San Diego San Diego CA 92103 USA Calif State Univ San Marcos Dept Comp Sci & Informat Syst San Marcos TX USA

ISBN: (纸本)9781450362597

parallel programming skills are becoming more popular due to the unprecedented boom in artificial intelligent and high-performance computing. programming assignments are widely used in parallel programming courses to measure student performance and expose students to constraints in real projects. However, due to the difficulty level of these assignments, many students struggle to write fully functional and adequately documented programs. To improve student performance, we implemented a moderated two-stage format for five course projects in a graduate-level introductory parallel programming class. Each project is divided into two stages where students complete the assignment individually without any collaboration in the first stage. Then students work in pairs to work on the same project in the second stage so they can review each other's work from the first stage and improve their programs collaboratively. For two of the five projects, a moderated meeting is conducted in between the two stages where the instructor moderated a group discussion on general issues raised by students. We found that students' performance improved from stage one to stage two. In addition, the two projects with a moderated meeting show better performance gains. This paper also examines students' perceptions of and experiences with the moderated two-stage projects. Students favor working on two-stage projects because they had a chance to discuss challenging concepts and the moderated discussion session tend to guide them to the correct path should they make mistakes in stage one.

关键词： Moderated Two-Stage Projects Collaborative Project parallel programming

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