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3rd International Workshop on High-Level Parallel Programming Models and Supportive Environments at the IPPS/SPDP 1998

作者： Guo, M Yamashita, Y Nakata, I Univ Tsukuba Tsukuba Ibaraki 305 Japan

ISBN: (纸本)0818684127

Array redistribution is required very often in programs on distributed memory parallel computers. It is essential to use efficient algorithms for redistribution, otherwise the performance of the programs may degrade considerably. In this paper, we focus on automatic generation of communication routines for multidimensional redistribution. The principal advantage of this work is to gain the ability to handle redistribution between arbitrary source and destination processor sets and between arbitrary source and destination distribution schemes. We have implemented these algorithms using Parallelware communication library. Some optimization techniques for our algorithms are also proposed in this paper. Experimental results show the efficiency and flexibility of our techniques compared to the other redistribution works.

关键词： parallelizing compiler HPF array redistribution automatic data distribution automatic parallelization and optimization

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Symbolic array dataflow analysis for array privatization and program parallelization

Symbolic array dataflow analysis for array privatization and...

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1995 ACM/IEEE Supercomputing Conference (SC 95)

作者： Gu, JJ Li, ZY Lee, G Univ of Minnesota Minneapolis United States

ISBN: (纸本)0897918622

Array dataflow information plays an important role for successful automatic parallelization of Fortran programs. This paper proposes a powerful symbolic array dataflow analysis to support array privatization and loop parallelization for programs with arbitrary control flow graphs and acyclic call graphs. Our scheme summarizes array access information using guarded array regions and propagates such regions over a Hierarchical Supergraph (HSG). The use of guards allows us to use the information in IF conditions to sharpen the array dataflow analysis and thereby to handle difficult cases which elude other existing techniques. The guarded array regions retain the simplicity of set operations for regular array regions in common cases, and they enhance regular array regions in complicated cases by using guards to handle complex symbolic expressions and array shapes. Scalar values that appear in array subscripts and loop limits are substituted on the fly during the array information propagation, which disambiguates the symbolic values precisely for set operations. We present efficient algorithms that implement our scheme. Initial experiments of applying our analysis to Perfect Benchmarks show promising results of improved array privatization. Copyright 1995 by the Association for Computing Machinery, Inc. (ACM).

关键词： parallelizing compiler array dataflow analysis interprocedural analysis array privatization symbolic analysis

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Efficient run-time parallelization for DO loops

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 1998年第1期14卷 237-253页

作者： Yang, CT Tseng, SS Hsieh, MH Kao, SH Natl Space Program Off ROCSAT Ground Segment Hsinchu 300 Taiwan Natl Tsing Hua Univ Dept Informat & Comp Sci Hsinchu 300 Taiwan

A run-time technique based on the inspector-executor scheme is proposed in this paper to find available parallelism on loops. Our inspector can determine the wavefronts by building a DEF-USE table for each loop of a program. Additionally, the process the inspector uses to find the wavefronts can be parallelized fully without any synchronization. Our executor executes loop iterations concurrently. For each wavefront, the auto-adapted function is used to get a tailored thread number instead of using a fixed number of thread for execution. Experimental results show that our new parallel inspector can handle complex data dependency patterns and significantly reduce the execution time.

关键词： run-time loop parallelization inspector executor parallelizing compiler multiprocessor systems

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Development and implementation of an interactive parallelization assistance tool for OpenMP: iPat/OMP

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2006年第2期E89D卷 399-407页

作者： Ishirara, M Honda, H Sato, M Univ Electrocommun Grad Sch Informat Syst Chofu Tokyo 1828585 Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki 3058577 Japan

iPat/OMP is an interactive parallelization assistance tool for OpenMP. In the present paper, we describe the design concept of iPat/OMP, the parallelization sequence achieved by the tool and its current implementation status. In addition, we present an evaluation of the performance of the implemented functionalities. The experimental results show that iPat/OMP can detect parallelism and create an appropriate OpenMP directive for several for-loops.

关键词： OpenMP interactive parallelization assistance tool parallelizing compiler human readability

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Implementing a dynamic processor allocation policy for multiprogrammed parallel applications in the Solaris™ operating system

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2001年第6期13卷 449-464页

作者： Yue, KK Lilja, DJ Univ Minnesota Minnesota Supercomp Inst Dept Elect & Comp Engn Minneapolis MN 55455 USA Sun Microsyst Inc Palo Alto CA 94303 USA

Parallel applications typically do not perform well in a multiprogrammed environment that uses time-sharing to allocate processor resources to the applications' parallel threads. Co-scheduling related parallel threads, or statically partitioning the system, often can reduce the applications' execution times, but at the expense of reducing the overall system utilization. To address this problem, there has been increasing interest in dynamically allocating processors to applications based on their resource demands and the dynamically varying system load. The Loop-Level Process Control (LLPC) policy (Yue K, Lilja D. Efficient execution of parallel applications in multiprogrammed multiprocessor systems. 10th International Parallel Processing Symposium, 1996;448-456) dynamically adjusts the number of threads an application is allowed to execute based on the application's available parallelism and the overall system load. This study demonstrates the feasibility of incorporating the LLPC strategy into an existing commercial operating system and parallelizing compiler and provides further evidence of the performance improvement that is possible using this dynamic allocation strategy. In this implementation, applications are automatically parallelized and enhanced with the appropriate LLPC hooks so that each application interacts with the modified version of the Solaris operating system. The parallelism of the applications are then dynamically adjusted automatically when they are executed in a multiprogrammed environment so that all applications obtain a fair share of the total processing resources. Copyright (C) 2001 John Wiley & Sons, Ltd.

关键词： multiprogramming process scheduling processor allocation operating system parallelizing compiler shared-memory multiprocessor performance measurement

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A compiling technique for dataflow machines - New algorithm for optimum translation from control flow graph into dataflow graph

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SYSTEMS AND COMPUTERS IN JAPAN 1996年第4期27卷 12-24页

作者： Yasue, T Muraoka, Y Member School of Science and Engineering Waseda University Tokyo Japan 169

In this paper an optimum algorithm to translate control flow graphs to dataflow graphs is proposed for dataflow execution of sequential programs. Some of the existing analysis methods restrict the specification of a program to be processed while others require a very high analysis cost. The algorithm proposed in this paper (CD translation algorithm), (1) with a very low cost, and (2) for any control structure that can be described by a control flow graph, (3) can generate dataflow programs that give an optimum dataflow execution, Furthermore, this proposed analysis algorithm is designed to handle task level control flow graphs as well as instruction level control flow graphs, which are accepted by the existing methods, so that optimum control is-possible for task level dataflow execution.

关键词： dataflow execution parallelizing compiler control dependency data dependency dataflow analysis

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Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture

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IEICE TRANSACTIONS ON ELECTRONICS 2003年第4期E86C卷 570-579页

作者： Kimura, K Kodaka, T Obata, M Kasahara, H Waseda Univ Adv Res Inst Sci & Engn Tokyo 1698555 Japan Waseda Univ Dept Elect Elect & Comp Engn Tokyo 1698555 Japan Adv Parallelizing Compiler Project Tokyo 1698555 Japan

This paper describes multigrain parallel processing on OSCAR (Optimally SCheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal, use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for overlapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed. simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3.84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.

关键词： chip multiprocessor multigrain parallel processing parallelizing compiler

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AUTOMATIC DATA AND COMPUTATION DECOMPOSITION FOR DISTRIBUTED-MEMORY MACHINES

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Parallel Processing Letters 1995年第4期5卷 539-550页

作者： QI NING VINCENT VAN DONGEN GUANG R. GAO Qi Ning is now affiliated with Convex Computer Corporation 3000 Waterview Parkway Richardson TX 75083-3851. Centre de Recherche Informatique de Montréal 1801 McGill Avenue Bureau 800 Montreal Quebec Canada H3A 2N4 Canada School of Computer Science McGill University Montreal Quebec Canada H3A 2A7 Canada

In this paper, we develop an automatic compile-time computation and data decomposition technique for distributed-memory machines. Our method handles complex programs containing perfect and non-perfect loop nests with or without loop-carried dependences. Applying our algorithms, a program will be divided into collections (called clusters) of loop nests, such that data redistributions are allowed only between the clusters. Within each cluster of loop nests, decomposition and data locality constraints are formulated as a system of homogeneous linear equations which is solved by polynomial time algorithms. Our algorithm can selectively relax data locality constraints within a cluster to achieve a balance between parallelism and data locality. Such relaxations are guided by exploiting the hierarchical program nesting structures from outer to inner nesting levels to keep the communications at a outer-most level possible.

关键词： Automatic loop parallelization parallelizing compiler data computation decomposition for distributed-memory machines

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UNIMODULARITY AND THE PARALLELIZATION OF LOOPS

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Parallel Processing Letters 1992年第2N03期2卷 273-281页

作者： MICHAEL BARNETT CHRISTIAN LENGAUER Laboratory for Applied Logic Department of Computer Science University of Idaho Moscow Idaho 83843 U.S.A. Fakultät für Mathematik und Informatik Universität Passau D–W8390 Passau Germany

The parallelization of loops can be made formal by basing it on an algebraic theory of loop transformations. In this theory, the concept of unimodularity arises. We discuss the pros and cons of insisting on unimodular... 详细信息

关键词： parallelizing compiler space-time transformation systolic array unimodularity

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DPART: AN AUTOMATIC DATA PARTITIONING SYSTEM FOR DISTRIBUTED MEMORY PARALLEL MACHINES

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Parallel Algorithms and Applications 1996年第3-4期9卷 205-212页

作者： Zhaohui Duan[a] Zhaoqing Zhang[a] [a] National Research Center for Intelligent Computing Systems Institute of Computing Technology Beijing PR China

One of the most intellectual steps in compiling for distributed memory parallel machines is to determine a suitable data partitioning scheme for a particular program. Most of the parallelizing compilers for these machines provide no or little support to the user in this difficult task. We have developed DPART, an automatic data partitioning system for Fortran 77 procedures. This paper describes the partitioning strategics of alignment, distribution, and processor layout in DPART. Finally we present experimental results for TRED2, DGEFA, and JACOBI procedures to demonstrate the effectiveness of this system.

关键词： Data partitioning distributed memory parallel machines parallelizing compiler

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