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Optimizing FORTRAN Programs for Hierarchical Memory Parallel Processing Systems

Journal of Computer Science & Technology 1993年第3期8卷 209-220页

作者：金国华陈福接 Department of Computer Science Changsha Institute of TechnologyChangsha 410073

Parallel loops account for the greatest amount of parallelism in numerical *** nested loops in parallel with low run-time overhead is thus very important for achieving high perform- ance in parallel processing ***,in parallel processing systems with caches or local memo- ries in memory hierarchies,“thrashing problem”may arise whenever data move back and forth between the caches or local memories in different processors. Previous techniques can only deal with the rather simple cases with one linear function in the perfect- ly nested *** this paper,we present a parallel program optimizing technique called hybrid loop inter- change(HLI)for the cases with multiple linear functions and loop carried data dependences in the nested *** HLI we can easily eliminate or reduce the thrashing phenomena without reducing the program parallelism.

关键词： Thrashing problem hierarchical memory cache parallelizing compiler hybrid loop interchange FORTRAN

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Array operation synthesis to optimize HPF programs on distributed memory machines

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2001年第4期61卷 467-500页

作者： Hwang, GH Lee, JK Ju, RDC Natl Chi Nan Univ Dept Informat Management Nantou Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30043 Taiwan Intel Corp Microprocessor Res Labs Santa Clara CA 95052 USA

An increasing number of programming languages;such as Fortran 90, HPF, and APL, provide a rich set of intrinsic array functions and array expressions. These constructs, which constitute an important part of data parallel languages, provide excellent opportunities for compiler optimizations. The synthesis of consecutive array operations or array expressions into a composite access function of the source arrays at compile time has been shown (A, T, Budd, ACM Trans. Programm. Lang, Syst. 6 (July 1984), 297-313;G. H. Hwang et al,, bz "Proc. of ACM SIGPLAN Conference on Principles and Practice of Parallel Programming, 1995," pp. 112-122) to be an effective scheme for optimizing programs on flat shared memory parallel architectures. It remains, however, to be studied how the synthesis scheme can be incorporated into optimizing HPF-like programs on distributed memory machines by taking into account communication costs. In this paper, we propose solutions to address this issue. We first show how to perform array operation synthesis on HPF programs, and we demonstrate its performance benefits on distributed memory machines with real applications. In addition, to prevent a situation we call "synthesis anomaly," we present an optimal solution to guide the array synthesis process on distributed memory machines. Due to the optimal problem being NP-hard, we further develop a practical strategy that compilers can use on distributed memory machines with HPF programs. Our synthesis engine is implemented as a Web-based tool, called Syntool, and experimental results show significant performance improvement over the base codes for HPF code fragments from real applications on parallel machines. Our experiments were performed on three distributed memory machines: an 8-node DEC Alpha Farm, a 16-node TBM SP-2, and a 16-node nCUBE/2. (C) 2001 Academic Press.

关键词： HPF compiler array operation synthesis distributed memory machines compiler optimization parallelizing compiler

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An object-oriented framework for loop parallelization

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JOURNAL OF SUPERCOMPUTING 1999年第1期13卷 57-69页

作者： Omori, Y Fukuda, A Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300101 Japan Wakayama Univ Fac Syst Engn Wakayama 6408441 Japan

Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The various choices of current and future parallel computer architectures as well as the cost of developing a parallelizing compiler make portability a very important design goal. Since the design of parallelizing compilers is considerably move complex than designing conventional compilers, it is very important to achieve both efficiency and portability. To meet this dual goal, we have investigated the application of object oriented design to parallelizing compilers. Our parallelizing compiler design is based on abstractions of intermediate representations of loops and their class definitions. In this paper, we address the problem of loop parallelization and propose a framework where the loop parallelization process is divided into three phases and the optimization of loops is performed via a cyclic application of these three phases. The class of each phase is hierarchically derived from intermediate representations of loops. This facilitates the portability of the resulting parallelizing compilers. Furthermore, one of the phases uses a reservation table of hardware resources in order to obtain optimized parallel programs for given hardware resources. The validation of the proposed framework is given through the application of the object oriented design on an example program which is then parallelized efficiently.

关键词： object-oriented design parallelizing compiler loop parallelization OMT portability

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Self adaptive run time scheduling for the automatic parallelization of loops with the C2μTC/SL compiler

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PARALLEL COMPUTING 2013年第10期39卷 603-614页

作者： Saougkos, Dimitris Manis, George Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece

In this paper we suggest a new approach for solving the hyperplane problem, also known as "wavefront" computation. In direct contrast to most approaches that reduce the problem to an integer programming one or use several heuristic approaches, we gather information at compile time and delegate the solution to run time. We present an adaptive technique which intuitively calculates which new threads will be able to be executed in the next computation cycle based on which threads are executed in the current one. Moving the solution to the run time environment provides us with higher versatility alongside a perfect solution of the underlying hyperplane pattern being discovered without the need to perform any prior calculations. The main contribution of this paper is the presentation of the self adaptive algorithm, an algorithm which does not need to know the tile size (which controls the granularity of parallelism) beforehand. Instead, the algorithm itself adapts the tile size while the program is running in order to achieve optimal efficiency. Experimental results show that if we have a sufficient number of parallel processing elements to diffuse the scheduler's workload, its overhead becomes low enough that it is overshadowed by the net gain in parallelism. For the implementation of the algorithm we suggest, and for our experimentations our parallelizing compiler C2 mu TC/SL is used, a C parallelizing compiler which maps sequential programs on the SVP processor and model. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Self-adaptive Run-time scheduling parallelizing compiler Multithreaded processing

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Loop Staggering,Loop Compacting:Restructuring Techniques for Thrashing Problem

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Journal of Computer Science & Technology 1993年第1期8卷 49-56页

作者：金国华杨学军陈福接 Dept.of Computer Science Changsha Institute of TechnologyChangsha 410073

Parallel loops account for the greatest amount of parallelism in numerical *** nested loops in parallel with low run-time overhead is thus very important for achieving high performance in parallel processing ***,in parallel processing systems with caches or local memories in memory hierarchies,“thrashing problem”may arise when data move back and forth frequently between the caches or local memories in different *** techniques associated with parallel compiler to solve the problem are not completely *** this paper,we present two restructuring techniques called loop staggering,loop staggering and compacting,with which we can not only eliminate the cache or local memory thrashing phenomena significantly,but also exploit the potential parallelism existing in outer serial *** staggering benefits the dynamic loop scheduling strategies,whereas loop staggering and compacting is good for static loop scheduling strategies,Our method especially benefits parallel programs,in which a parallel loop is enclosed by a serial loop and array elements are repeatedly used in the different iterations of the parallel loop.

关键词： parallelizing compiler loop staggering loop compacting thrashing problem cache

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The efficient computation of ownership sets in HPF

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2001年第8期12卷 769-788页

作者： Joisha, PG Banerjee, P Northwestern Univ Inst Technol Ctr Parallel & Distributed Comp Dept Elect & Comp Engn Evanston IL 60208 USA

Ownership sets are fundamental to the partitioning of program computations across processors by the owner-computes rule. These sets arise due to the mapping of arrays onto processors. In this paper, we focus on how ownership sets can be efficiently determined in the context of the HPF language and show how the structure of these sets can be symbolically characterized in the presence of arbitrary array alignment and array distribution directives. Our starting point is a system of equalities and inequalities due to Ancourt et al. [1] that captures the array mapping problem in HPF. We arrive at a refined system that enables us to efficiently solve for the ownership set using the Fourier-Motzkin Elimination technique and that requires the course vector as the only auxiliary vector. The formulation makes it possible to enumerate the elements of the ownership set exactly once, a feature that is very beneficial when such sets are applied to handle Do loops qualified by HPF's INDEPENDENT directive. We develop important and general properties pertaining to HPF alignments and distributions and show how they can be used to eliminate redundant communication due to array replication. Polynomial-time schemes that determine whether the ownership set of a particular processor, with respect to some array, is the empty set or whether the ownership set of every processor, with respect to some array, is the empty set, are presented. We show how distribution directives with unspecified processor meshes can be efficiently handled at compile time. We also show how to avoid the generation of communication code when pairs of array references are ultimately mapped onto the same processors. Experimental data demonstrating the improved code performance that the latter optimization enables is presented and discussed.

关键词： HPF array alignment array distribution ownership set Fourier-Motzkin Elimination technique parallelizing compiler

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Using basis dependence distance vectors in the modified Floyd-Warshall algorithm

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JOURNAL OF COMBINATORIAL OPTIMIZATION 2015年第2期30卷 253-275页

作者： Bielecki, Wodzimierz Kraska, Krzysztof Klimek, Tomasz West Pomeranian Univ Technol Fac Comp Sci & Informat Technol PL-71210 Szczecin Poland

In this paper, we present a modified Floyd-Warshall algorithm, where the most time-consuming part-calculating transitive closure describing self-dependences for each loop statement-is computed applying basis dependence distance vectors derived from all vectors describing self-dependences. We demonstrate that the presented approach reduces the transitive closure calculation time for parameterized graphs representing all dependences in the loop in comparison with that yielded by means of techniques implemented in the Omega and ISL libraries. This increases the applicability scope of techniques based on transitive closure of dependence graphs and being aimed at building optimizing compilers. Experimental results for NASA Parallel Benchmarks are discussed.

关键词： Basis dependence vectors Transitive closure Floyd-Warshall algorithm Arbitrarily nested loop parallelizing compiler

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COMPILING COMMUNICATION-EFFICIENT PROGRAMS FOR MASSIVELY PARALLEL MACHINES

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1991年第3期2卷 361-376页

作者： LI, JK CHEN, M YALE UNIV DEPT COMP SCISYST & PROGRAMMING LANGUAGES GRPNEW HAVENCT 06520

This paper presents a method of generating parallel target code with explicit communication for massively parallel, distributed-memory machines. The source programs are shared-memory parallel programs with explicit control structures. The method contains four main parts: 1) analysis: extracting syntactic reference patterns from a program with shared address space, 2) pattern matching: selecting appropriate communication routines, 3) scheduling: placing these routines in appropriate locations in the target program text, and 4) synchronization: setting up correct conditions for invoking these routines. We use an explicit communication metric to guide the selection of data layout strategies.

关键词： COORDINATION DATA LAYOUT DISTRIBUTED-MEMORY INTERPROCESSOR COMMUNICATION MASSIVELY PARALLEL MACHINE parallelizing compiler REFERENCE PATTERN RUN-TIME SYSTEM SCHEDULING SHARED ADDRESS SPACE SHARED-MEMORY SYNCHRONIZATION

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Non-linear array data dependence test

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JOURNAL OF SYSTEMS AND SOFTWARE 2001年第2期57卷 145-154页

作者： Huang, TC Yang, CM Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 80424 Taiwan

Data dependence analysis is the most essential process while parallelizing a sequential program. Most current data dependence tests cannot handle array subscripts that are non-linear expressions. In this paper, we present a new parallelization algorithm, called non-linear array subscripts (NLA) test, to deal with non-linear or complex array subscripts. In this scheme, the iterations subject to loop-carried dependence are scheduled into different wavefronts, while the iterations with no loop-carried dependence are assigned into the same wavefront. Based on the wavefront information, the original loop is then transformed into parallel code. Our experimental results on shared-memory parallel machines HP SPP2000 and ALR Quad6 prove the high effectiveness of the NLA test. (C) 2001 Elsevier Science Inc. All rights reserved.

关键词： data dependence test non-linear array subscripts parallelizing compiler

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Power-aware compiler controllable chip multiprocessor

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IEICE TRANSACTIONS ON ELECTRONICS 2008年第4期E91C卷 432-439页

作者： Shikano, Hiroaki Shirako, Jun Wada, Yasutaka Kimura, Keiji Kasahara, Hironori Waseda Univ Dept Comp Sci Tokyo 1698555 Japan Hitachi Ltd Cent Res Lab Kokubunji Tokyo 1858601 Japan

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

关键词： chip multiprocessor parallelizing compiler frequency and voltage control

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