检索结果-内蒙古大学图书馆

MICROPROCESSING AND MICROPROGRAMMING 1995年第5-6期41卷 391-408页

作者： KNEIP, J OHMACHT, M RONNER, K PIRSCH, P Laboratorium für Informationstechnologie Universität Hannover Schneiderberg 32 D-30167 Hannover Germany

A highly parallel single-chip image signal processor architecture has been derived by analysis of image processing algorithms. Available levels of parallelism and their associated demands on data access, control and complexity of operations were taken into account. The RISC-architecture, called ''HiPAR-DSP'', consists of a control unit, 16 parallel ASIMD-controlled datapaths with autonomous addressing and instruction selection capability, a local data cache per data path, a shared memory with matrix type data access and a powerful DMA-unit. The proposed architecture was designed by assessing the results of an analysis of characteristic algorithm properties with respect to their inherent parallelization resources, achievable speed up and implementation costs. This resulted in a proper balance between the degree of parallelism and flexibility, leading to a high performance for a wide field of applications. Additional measures were taken to support an efficient high level programmability of the processor. This was achieved by the concurrent implementation of special architectural features and a C++-programming environment. It consists of an adaptation of the GNU C++-compiler and an optimizing assembler, supporting all levels of concurrence offered by the hardware. While most levels of parallelization are kept invisible to the programmer, data-level parallelism is expressed by the programmer using special new data types added to the standard C/C++-data-types. A sustained performance of about 2.0 Gigaoperations per second is achieved by the 100 MHz clocked processor for numerous image processing algorithms, leading to a processing time e.g. for a normalized correlation of a 512 x 512 image with a 32 x 32 correlation mask of 450 ms. Thus, a performance is achieved with a programmable parallel processor architecture that hitherto required the application of a dedicated integrated circuit.

关键词： PARALLEL VLSI RISC PROCESSOR SHARED MEMORY ARCHITECTURE AUTONOMOUS SIMD CONTROLLING IMAGE PROCESSING parallelizing compiler PARALLEL LANGUAGE EXTENSION

来源：评论

学校读者我要写书评

暂无评论

Time stamp algorithms for runtime parallelization of DOACROSS loops with dynamic dependences

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2001年第5期12卷 433-450页

作者： Xu, CZ Chaudhary, V Wayne State Univ Dept Elect & Comp Engn Detroit MI 48202 USA

This paper presents a time stamp algorithm for runtime parallelization of general DOACROSS loops that have indirect access patterns. The algorithm follows the INSPECTOR/EXECUTOR scheme and exploits parallelism at a fine-grained memory reference level. It features a parallel inspector and improves upon previous algorithms of the same generality by exploiting parallelism among consecutive reads of the same memory element. Two variants of the algorithm are considered: One allows partially concurrent reads (PCR) and the other allows fully concurrent reads (FCR). Analyses of their time complexities derive a necessary condition with respect to the iteration workload for runtime parallelization. Experimental results for a Gaussian elimination loop, as well as an extensive set of synthetic loops on a 12-way SMP server, show that the time stamp algorithms outperform iteration-level parallelization techniques in most test cases and gain speedups over sequential execution for loops that have heavy iteration workloads. The PCR algorithm performs best because it makes a better trade-off between maximizing the parallelism and minimizing the analysis overhead. For loops with light or unknown iteration loads, an alternative speculative runtime parallelization technique is preferred.

关键词： compiler parallelizing compiler runtime support inspector-executor doacross loop dynamic dependence

来源：评论

学校读者我要写书评

暂无评论

Scheduling GEN_BLOCK array redistribution

引用

JOURNAL OF SUPERCOMPUTING 2002年第3期22卷 251-267页

作者： Yook, HG Park, MS Samsung Elect Co Ltd Suwon South Korea Korea Univ Dept Comp Engn & Sci Seoul South Korea

This article is devoted to the redistribution of arrays that are distributed in a GEN_BLOCK fashion over a processor grid. While GEN_BLOCK redistribution is essential for load balancing, prior research about redistribution has been focused on block-cyclic redistribution. The proposed scheduling algorithm exploits a spatial locality in message passing from a seemingly irregular array redistribution. The algorithm attempts to obtain near optimal scheduling by trying to minimize communication step size and the number of steps. According to experiments on CRAY T3E and IBM SP2, the algorithm shows good performance in typical distributed memory machines.

关键词： HPF parallelizing compiler array redistribution GEN_BLOCK

来源：评论

学校读者我要写书评

暂无评论

Language and compiler design for streaming applications

引用

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2005年第2-3期33卷 261-278页

作者： Amarasinghe, S Gordon, MI Karczmarek, M Lin, J Maze, D Rabbah, RM Thies, W MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

High-performance streaming applications are a new and distinct domain of programs that is increasingly important. The StreamIt language provides novel high-level representations to improve programmer productivity and program robustness within the streaming domain. At the same time, the StreamIt compiler aims to improve the performance of streaming applications via stream-specific analysis and optimizations. In this paper, we motivate, describes and justify the StreamIt language which include a structured model of streams, a messaging system for control, and a natural textual syntax.

关键词： stream computing StreamIt parallelizing compiler tiled-processor architectures productivity

来源：评论

学校读者我要写书评

暂无评论

Segmented alignment: An enhanced model to align data parallel programs of HPF

引用

JOURNAL OF SUPERCOMPUTING 2003年第1期25卷 17-41页

作者： Hwang, GH Chen, GW Lee, JK Ju, RDC Natl Taiwan Normal Univ Dept Informat & Comp Educ Taipei Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30043 Taiwan Intel Corp Microprocessor Res Labs Santa Clara CA 95052 USA

In this paper, we propose a new automatic data alignment model called segmented alignment. The conventional data alignment model, such as that used in High-Performance Fortran (HPF), aligns arrays with the whole index domain. The principle of our proposed segmented alignment is to allow alignment relations within delimited index domains. We first provide motivating examples to illustrate how code fragments of HPF with EOSHIFT or CSHIFT operations, or produced by synthesis operations can benefit from our enhanced alignment scheme. Second, we show that this new model can be implemented in HPF-like languages by adding WHEN and IN constructs to them. In addition, we show that the new proposed schemes for WHEN and IN constructs can be emulated using standard HPF syntax. Finally, we address issues related to automatic data alignment for the new proposed model, and present an algorithm to automatically align programs using our segmented alignment scheme. Since the optimal algorithm to do this is NP-hard, a practical heuristic is also given. Our experiments were performed on a DEC Alpha Farm with HPF environments. Our experiments confirm our theory that our proposed alignment scheme can significantly enhance not only the performance of HPF code fragments with EOSHIFT or CSHIFT operations, but also that of codes produced by synthesis operations.

关键词： automatic array alignment segmented alignment HPF compilers distributed-memory machines compiler optimization parallelizing compiler

来源：评论

学校读者我要写书评

暂无评论

Predecessor/successor approach for high-performance run-time wavefront scheduling

引用

INFORMATION SCIENCES 2006年第7期176卷 845-860页

作者： Huang, TC Hsu, PH Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 804 Taiwan Cheng Shiu Inst Technol Dept Elect Engn Kaohsiung 833 Taiwan

Most scientific applications rely on parallel Multiprocessor computing to enhance Performance. However, the irregular loops within these applications obstruct the parallefism analysis at compile-time. Rauchwerger et al. presented a run-time method to extract the hidden parallelism in a program using dependence chains. The relative overhead degrades this approach's performance due to the mass storage requirement and huge array reference processing. In this Study, a new predecessor/successor approach is developed in which high-level predecessor/successor information is recorded and processed efficiently. A predecessor/successor table is constructed first in the inspector phase so that only the successor iterations in the current wavefront need to be examined, instead of the entire loop iterations during wavefront scheduling. Usually, the performance of dependence chain approach degrades dramatically for a hot-spot access pattern, but Our scheme works very efficiently in this case. The experimental results using synthetic code and real programs are presented to prove the superiority of the proposed approach. (c) 2005 Elsevier Inc. All rights reserved.

关键词： parallelizing compiler dependence chain loop parallelization inspector/executor wavefront scheduling

来源：评论

学校读者我要写书评

暂无评论

Efficient algorithms for data distribution on distributed memory parallel computers

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1997年第8期8卷 825-839页

作者： Lee, PZ Institute of Information Science Taipei Taiwan

Data distribution has been one of the most important research topics in parallelizing compilers for distributed memory parallel computers. Good data distribution schema should consider both the computation load balance and the communication overhead. In this paper, we show that data redistribution is necessary for executing a sequence of Do-loops if the communication cost due to performing this sequence of Do-loops is larger than a threshold value. Based on this observation, we can prune the searching space and derive efficient dynamic programming algorithms for determining effective data distribution schema to execute a sequence of Do-loops with a general structure. Experimental studies on a 32-node nCUBE-2 computer are also presented.

关键词： component alignment data distribution distributed memory computer Do-loops dynamic programming algorithm for data distribution parallelizing compiler

来源：评论

学校读者我要写书评

暂无评论

compiler techniques for the distribution of data and computation

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2003年第6期14卷 545-562页

作者： Navarro, A Zapata, E Padua, D Univ Malaga Dept Comp Architecture Malaga 29080 Spain Univ Illinois Dept Comp Sci Digital Comp Lab 3318 Urbana IL 61801 USA

This paper presents a new method that can be applied by a parallelizing compiler to find, without user intervention, the iteration and data decompositions that minimize communication and load imbalance overheads in parallel programs targeted at NUMA architectures. One of the key ingredients in our approach is the representation of locality as a Locality-Communication Graph (LCG) and the formulation of the compiler technique as a Mixed Integer Nonlinear Programming (MINLP) optimization problem on this graph. The objective function and constraints of the optimization problem model communication costs and load imbalance. The solution to this optimization problem is a decomposition that minimizes the parallel execution overhead. This paper summarizes the process of how the compiler extracts the locality information from a nonannotated code and focuses on how this compiler can derive the optimization problem, solve it, and generate the parallel code with the automatically selected iteration and data distributions. In addition, we include a discussion about our model and the solutions-the decompositions-that it provides. The approach presented in the paper is evaluated using several benchmarks. The experimental results demonstrate that the MINLP formulation does not increase compilation time significantly and that our framework generates very efficient iteration/data distributions for a variety of NUMA machines.

关键词： parallelizing compiler locality analysis load balancing communication pattern mixed integer nonlinear programming

来源：评论

学校读者我要写书评

暂无评论

New shape analysis and interprocedural techniques for automatic parallelization of C codes

引用

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2002年第1期30卷 37-64页

作者： Corbera, F Asenjo, R Zapata, E Univ Malaga Comp Architecture Dept E-29080 Malaga Spain

Automatic parallelization of codes with complex data structures is becoming very important. These complex, and often recursive, data structures are widely used in scientific computing. Shape analysis is one of the key steps in the automatic parallelization of such codes. In this paper we extend the Static Shape Graph (SSG) method to enable the successful and accurate detection of complex doubly-linked structures. We have also included an interprocedural analysis in our framework. These techniques have been implemented in a compiler, which has been validated for several C codes. In particular, we present the results the compiler achieves for the C sparse LU factorization algorithm and for a recursive code generating a tree data structure. The output SSG perfectly describes the complex data structure used in these codes.

关键词： parallelizing compiler shape analysis pointers recursive data structures shape graphs

来源：评论

学校读者我要写书评

暂无评论

An intelligent parallel loop scheduling for parallelizing compilers

引用

JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2000年第2期16卷 169-200页

作者： Fann, YW Yang, CT Tseng, SS Tsai, CJ Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan Natl Space Program Off ROCSAT Ground Syst Sect Hsinchu 300 Taiwan

In this paper we propose a knowledge-based approach to solving loop-scheduling problems. A rule-based system, called IPLS, is developed by combining a repertory grid and an attribute ordering table to construct a knowledge base. IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigning parallel loops to multiprocessors to achieve significant speedup. Because more attributes are proposed, the accuracy of selection of an appropriate scheduling method is improved. In addition, the refined IPLS system can automatically adjust the attributes in the knowledge base according to profile information;therefore, IPLS has the capability of feedback learning. The experimental results show that our approach can achieve greater speedup on multiprocessor systems than can others.

关键词： parallelizing compiler parallel loop scheduling knowledge-based system multiprocessor systems speedup

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：