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3rd International Conference on Applications in Information Technology (ICAIT)

作者： Steinberg, Boris Baglij, Anton Petrenko, Victor Burkhovetskiy, Victor Steinberg, Oleg Metelica, Elena Southern Fed Univ Rostov Na Donu Russia

ISBN: (纸本)9781450365161

The article describes new facilities for program optimization and parallelization, work-in-progress modifications of previously implemented program transformations and compiler libraries, and future development of Optimizing parallelizing system (OPS) including opening its source code on GitHub. These new facilities, such as dialog-based optimization and parallelization, user-friendly program dependency visualization (which is needed for high-quality analyzers), parallel code generation for accelerators (GPUs, DSPs, FPGAs, or high performance clusters), are made possible by the fact, that OPS uses high-level intermediate representation as opposed to low-level intermediate representation used in popular compilers.

关键词： parallelizing compiler high-level intermediate representation interactive compiler tiling data locality program transformations reconfigurable architectures

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parallelizing compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

Parallelizing Compiler Framework and API for Power Reduction...

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23rd International Workshop on Languages and compilers for Parallel Computing (LCPC 2010)

作者： Hayashi, Akihiro Wada, Yasutaka Watanabe, Takeshi Sekiguchi, Takeshi Mase, Masayoshi Shirako, Jun Kimura, Keiji Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Shinjuku Ku Tokyo Japan

ISBN: (纸本)9783642195945

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

关键词： Heterogeneous Multicore parallelizing compiler API

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Parallelization for multi-dimensional loops with non-uniform dependences

IAENG International Journal of Computer Science

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IAENG International Journal of Computer Science 2018年第1期45卷 17-21页

作者： Jeong, Sam-Jin Division of Information and Communication Engineering Baekseok University #76 Munam-ro Cheonan Chungnam330-704 Korea Republic of

This paper presents two enhanced partitioning algorithms in order to improve parallelization of multi-dimensional loops with flow and anti-dependences Using distance of the first dependence, we show the first general enhanced algorithm of single-loops with both flow and anti-dependences. Using the first algorithm, loop interchanging method, and cycle shrinking method, we present parallelization of nested loops with simple subscripts. Using the second algorithm, we also present parallelization to multi-dimensional loops with both flow and anti-dependences. Our two presented algorithms show enhanced loop parallelization of multi-dimensional loops with both dependences. We will improve our proposed algorithms for multi-dimensional space with multiple dependences.

关键词： Loop transformation Multi-dimensional loops Multiple dependences Non-uniform dependence parallelizing compiler

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Automatic Local Memory Management for Multicores Having Global Address Space 1

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29th International Workshop on Languages and compilers for Parallel Computing (LCPC)

作者： Yamamoto, Kouhei Shirakawa, Tomoya Oki, Yoshitake Yoshida, Akimasa Kimura, Keiji Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Tokyo Japan Meiji Univ Grad Sch Adv Math Sci Tokyo Japan

ISBN: (数字)9783319527093

ISBN: (纸本)9783319527093;9783319527086

Embedded multicore processors for hard real-time applications like automobile engine control require the usage of local memory on each processor core to precisely meet the real-time deadline constraints, since cache memory cannot satisfy the deadline requirements due to cache misses. To utilize local memory, programmers or compilers need to explicitly manage data movement and data replacement for local memory considering the limited size. However, such management is extremely difficult and time consuming for programmers. This paper proposes an automatic local memory management method by compilers through (i) multi-dimensional data decomposition techniques to fit working sets onto limited size local memory (ii) suitable block management structures, called Adjustable Blocks, to create application specific fixed size data transfer blocks (iii) multi-dimensional templates to preserve the original multi-dimensional representations of the decomposed multi-dimensional data that are mapped onto one-dimensional Adjustable Blocks (iv) block replacement policies from liveness analysis of the decomposed data, and (v) code size reduction schemes to generate shorter codes. The proposed local memory management method is implemented on the OSCAR multi-grain and multi-platform compiler and evaluated on the Renesas RP2 8 core embedded homogeneous multicore processor equipped with local and shared memory. Evaluations on 5 programs including multimedia and scientific applications show promising results. For instance, speedups on 8 cores compared to single core execution using off-chip shared memory on an AAC encoder program, a MPEG2 encoder program, Tomcatv, and Swim are improved from 7.14 to 20.12, 1.97 to 7.59, 5.73 to 7.38, and 7.40 to 11.30, respectively, when using local memory with the proposed method. These evaluations indicate the usefulness and the validity of the proposed local memory management method on real embedded multicore processors.

关键词： parallelizing compiler Local memory management Multicore Global address space DMA Data decomposition

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How OPS (Optimizing parallelizing System) May be Useful for Clang 17

How OPS (Optimizing Parallelizing System) May be Useful for ...

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13th Central and Eastern European Software Engineering Conference in Russia (CEE-SECR)

作者： Gervich, Lev R. Guda, Sergey A. Dubrov, Denis V. Ibragimov, Ruslan A. Metelitsa, Elena A. Mikhailuts, Yury M. Paterikin, Artyom E. Petrenko, Victor V. Skapenko, Ilya R. Steinberg, Boris Ya. Steinberg, Oleg B. Yakovlev, Vladislav A. Yurushkin, Mikhail V. Southern Fed Univ Inst Math Mech & Comp Sci Rostov Na Donu Russia

ISBN: (纸本)9781450363969

In this work, the perspective of using Optimizing parallelizing System (http://***/en/) together with Clang compiler is considered. The converters from Clang intermediate representation (Clang AST) to OPS intermediate representation and back are described. The advantages of high-level internal representation of OPS over register-based LLVM and GCC internal representations in the problems of code generation for non-standard architectures are described. The capability of code generation for computational systems with distributed memory (for example, compute clusters), as well as graphical and FPGA accelerators from OPS internal representation is considered. The promising projects of automatic code acceleration that are being developed on the base of OPS are described. OPS source code has been gradually moved to open access since August 2017 (https://***/OpsGroup/open-ops).

关键词： parallelizing compiler internal program representation graphic accelerator FPGA accelerator dialog parallelization

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Automatic Generation of OpenCL Code for ARM Architectures 22nd

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22nd International European Conference on Parallel and Distributed Computing (Euro-Par)

作者： Afonso, Sergio Acosta, Alejandro Almeida, Francisco Univ La Laguna San Cristobal De Laguna Spain

ISBN: (纸本)9783319589435;9783319589428

The efficient exploitation of the increasing computational capabilities of mobile devices is still a challenge. The heterogeneity of Systems on Chip (SoC) makes necessary a very specific knowledge of their hardware in order to harness their full potential. OpenCL is a well known standard for cross-platform usage of accelerator devices. We follow an annotation-based approach for solving the problem of high development cost of OpenCL programming for mobile devices. With our approach, the programmer can select from different programming models the one that offers the best performance for each section of the application. Computational results show that our automatically-generated OpenCL code can outperform Renderscript when running on the GPU of Android devices, making it the best choice for a range of parallel algorithms.

关键词： parallelizing compiler Source-to-source translation Annotation based OpenCL Android ARM

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Automatic Acceleration of Stencil Codes in Android Devices 17th

Automatic Acceleration of Stencil Codes in Android Devices

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17th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP)

作者： Afonso, Ergio Acosta, Alejandro Almeida, Francisco Univ La Laguna San Cristobal De La Lagu Spain

ISBN: (纸本)9783319654829;9783319654812

The increase of performance in handheld devices due to their widespread adoption has required the integration of several distinct kinds of processor in a single chip. These technologies have turned current Systems on Chip into heterogeneous platforms. Stencil codes are a family of algorithms that appear in many relevant scientific and image processing codes. In order to improve the performance of these algorithms in heterogeneous platforms, the usage of accelerators is very important but, for a mobile applications developer, the development cost is very high. We propose a methodology, based in our framework Paralldroid, for automatically generating accelerated implementations of several well-known representative stencil codes. The performance of these codes has also been measured in order to demonstrate how Paralldroid is able to accelerate code without extensive or complex modifications. Results show great performance improvements for few code modifications.

关键词： Android OpenCL Stencil code Source-to-source translation parallelizing compiler Renderscript

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Automatic Computer System Characterization for a parallelizing compiler

Automatic Computer System Characterization for a Parallelizi...

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IEEE International Conference on Cluster Computing (CLUSTER)

作者： Sussman, Alan Lo, Norman Anderson, Timothy Univ Maryland UMIACS College Pk MD 20742 USA BAE Syst Electron Solutions Burlington MA 01803 USA

ISBN: (纸本)9780769545165

Effectively utilizing the compute power of modern multi-core machines is a challenging task for a programmer. Automated extraction of shared memory parallelism via powerful compiler transformations and optimizations is one means to such a goal. However, the effectiveness of such transformations is tied to detailed characteristics of the target computer system. In this paper, we describe an automated system for capturing such computer system characteristics that is based on prior work on various parts of the overall problem. The system characteristics measured include the number of available compute elements available to run threads, multiple memory hierarchy parameters, and functional unit latencies and bandwidths. We show experimental results on a wide range of compute platforms that validate the effectiveness of the overall approach.

关键词： Benchmark testing Computers Context Instruction sets Size measurement Synchronization parallelizing compiler system characterization

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Code Generation for Distributed-Memory Architectures

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COMPUTER JOURNAL 2016年第1期59卷 119-132页

作者： Zhao, Jie Zhao, Rongcai Xu, Jinchen Natl Digital Switching Syst Engn & Technol Res Ct Zhengzhou 450001 Peoples R China State Key Lab Math Engn & Adv Comp Zhengzhou 450001 Peoples R China

Compiling for distributed-memory architectures comprise two main phases. The first phase is to determine computation and data composition. In the 1990s, a great deal of work addressed this problem. The second phase is code generation. However, there is still no effective solution to this problem. Existing methods try to generate codes on the basis of computation and data composition. To enhance the performance of generated codes, various communication optimizations are introduced since communication is one of the main factors degrading the performance. These approaches would bring redundant communication data, as they did not optimize communications jointly with code generation. In this paper, we propose a novel code generation technique for distributed-memory architectures. First, we determine the communication sender and receiver by traversing a loop-based tree structure. To support message aggregation, we find the most appropriate point to insert a message. Secondly, we construct the communication set by proposing some code generation rules, and prove their correctness and accuracy. Redundant communication is thus eliminated. Also, we have evaluated some programs ranging from micro-kernels to applications in NAS parallel benchmarks, and have compared the performance with their message passing interface (MPI), High Performance Fortran (HPF) and Unified Parallel C (UPC) versions. Compared with these versions, our compiler can generate fewer communication points. The generated codes of outperform the HPF and UPC versions and the state-of-the-art, and the average performance can reach 70% of the hand-coded MPI programs.

关键词： parallelizing compiler code generation MPI message aggregation

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A High Performance Computing Framework for Data Mining 23

A High Performance Computing Framework for Data Mining

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23rd Annual IEEE International Conference on High Performance Computing, Data, and Analytics (HiPCW)

作者： Goyal, Navneet Balasubramaniam, Sundar Goyal, Poonam Islam, Saiyedul Sati, Mohit Birla Inst Technol & Sci Pilani Dept Comp Sci & Informat Syst Adv Data Analyt & Parallel Technol Lab Pilani Rajasthan India

ISBN: (纸本)9781509057733

Mining large data sets is no longer the prerogative of computer scientists - specialists in a wide variety of domains are performing analytics as a day-to-day activity. Often such analyses are specific to the domain and analysts are required to devise new algorithms or techniques. For such scenarios, providing a high-level programming environment that delivers high performance on clusters is a challenge. We propose a framework that supports high-level programming using domain abstractions in data mining while delivering scalable performance on commodity clusters i.e. clusters of multi-core workstations. This framework includes a domain specific programming language, DWARF, to enable data mining specialists to rapidly prototype algorithms. DWARF is supported by a compiler that automatically parallelizes code by identifying domain specific patterns and translating them to parallel code that exploits data parallelism and task parallelism. The compiler generates code for a hybrid virtual machine supporting distributed memory model at the top level and shared memory model nested within. The code generated by the compiler can be scheduled on commodity clusters. We compare the proposed framework with other frameworks commonly used for data mining on distributed platforms.

关键词： Big Data Analytics Data Mining Domain Specific Language High Performance Computing parallelizing compiler

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