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5th International Young Scientist Conference on Computational Science (YSC)

作者： Steinberg, Boris Ya. Bugliy, Anton P. Dubrov, Denis V. Mikhailuts, Yury V. Steinberg, Oleg B. Steinberg, Roman B. Southern Fed Univ Rostov Na Donu Russia

In the following work, a project for compiler that maps program loops onto a processor with programmable accelerator is presented. The processor with programmable architecture could be a system on a chip containing regular computational cores as well as a programmable circuit. A classification of loops according to information dependencies is suggested. For each loop class, the possibility and method for automatic organization of hardware support with an FPGA are examined. The compiler under study differs from the regular ones for the presence of a converter from C to the hardware description language as well as a driver library for data transfer between a CPU and accelerator.

关键词： reconfigurable architecture pipeline computations high-level synthesis parallelizing compiler high-level internal representation FPGA HDL

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Developing a High-Level Language compiler for a Computer with Programmable Architecture 16

Developing a High-Level Language Compiler for a Computer wit...

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12th Central and Eastern European Software Engineering Conference in Russia

作者： Steinberg, Boris Ya. Bugliy, Anton P. Dubrov, Denis V. Mikhailuts, Yury V. Steinberg, Roman B. Southern Fed Univ II Vorovich Inst Math Mech & Comp Sci Milchakov St 8a Rostov Na Donu 344090 Russia

ISBN: (纸本)9781450348843

The following work describes a project development of the C compiler for computing systems with programmable architectures. The compiler has been implemented on the base of OPS (Optimizing parallelizing System, http://***) and a converter of C language into VHDL (C2HDL). An example of the compiler use has been presented in the article.

关键词： Reconfigurable computations pipeline computing high-level synthesis parallelizing compiler high-level internal representation HDL FPGA MI

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A Project of compiler for a Processor with Programmable Accelerator

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Procedia Computer Science 2016年 101卷 435-438页

作者： Boris Ya. Steinberg Anton P. Bugliy Denis V. Dubrov Yury V. Mikhailuts Oleg B. Steinberg Roman B. Steinberg Southern Federal University Rostov-on-Don Russian Federation

关键词： reconfigurable architecture pipeline computations high-level synthesis parallelizing compiler high-level internal representation FPGA HDL

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An improved nonlinear data dependence test

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JOURNAL OF SUPERCOMPUTING 2015年第1期71卷 340-368页

作者： Zhao, Jie Zhao, Rongcai Chen, Xi Zhao, Bo State Key Lab Math Engn & Adv Comp Wuxi 214125 Peoples R China

To further parallelize large-scale nonlinear scientific computing applications, some data dependence techniques for nonlinear subscripts, especially for quadratic subscripts, were proposed in the past. The quadratic programming (QP) test and polynomial variable interval (PVI) test are two representative techniques. The QP test, which serves as an exact but time-consuming technique, always gives conservative results when the coefficient matrix of the quadratic terms is not positive semi-definite, while the PVI test will lose efficiency when there exist mixed polynomials in the dependence equation. Focusing on the dependences caused by quadratic subscripts in nonlinear and irregular programs, we propose an improved nonlinear data dependence test in this paper. We first normalize a quadratic equation which is written in a general form, and determine whether the canonical equation is integer solvable in the region of interest based on the interval equation theory. Experimental results show that, compared with the QP test, our method maintains a much lower time complexity. Furthermore, it can detect more general dependences than other dependence testing methods like the PVI test in terms of quadratic subscripts.

关键词： parallelizing compiler Data dependence test Nonlinear subscript Interval equation

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Using basis dependence distance vectors in the modified Floyd-Warshall algorithm

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JOURNAL OF COMBINATORIAL OPTIMIZATION 2015年第2期30卷 253-275页

作者： Bielecki, Wodzimierz Kraska, Krzysztof Klimek, Tomasz West Pomeranian Univ Technol Fac Comp Sci & Informat Technol PL-71210 Szczecin Poland

In this paper, we present a modified Floyd-Warshall algorithm, where the most time-consuming part-calculating transitive closure describing self-dependences for each loop statement-is computed applying basis dependence distance vectors derived from all vectors describing self-dependences. We demonstrate that the presented approach reduces the transitive closure calculation time for parameterized graphs representing all dependences in the loop in comparison with that yielded by means of techniques implemented in the Omega and ISL libraries. This increases the applicability scope of techniques based on transitive closure of dependence graphs and being aimed at building optimizing compilers. Experimental results for NASA Parallel Benchmarks are discussed.

关键词： Basis dependence vectors Transitive closure Floyd-Warshall algorithm Arbitrarily nested loop parallelizing compiler

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Automatic High-Level Programs Mapping onto Programmable Architectures 13th

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13th International Conference on Parallel Computing Technologies (PaCT)

作者： Steinberg, Boris Ya Dubrov, Denis V. Mikhailuts, Yury Roshal, Alexander S. Steinberg, Roman B. Southern Fed Univ Rostov Na Donu Russia

ISBN: (纸本)9783319219097;9783319219080

Atechnique for automatic high-level C program mapping onto compute systems with programmable pipeline architecture is presented in this article. An example of such a system could be a CPU with an FPGA accelerator or the corresponding system on a chip. The mapping is implemented on the base of Optimizing parallelizing System (***) and C2HDL converter from C to the hardware description language (VHDL). HDL code generating from OPS internal representation would allow to utilize the user dialog to generate a family of equivalent chips, from which the user could select the most suitable one for various characteristics. The development of the current work would allow to create for the first time the C language compiler for the programmable pipeline architecture.

关键词： Reconfigurable computing Pipeline computing High-level synthesis parallelizing compiler High level internal representation HDL FPGA

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Self adaptive run time scheduling for the automatic parallelization of loops with the C2μTC/SL compiler

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PARALLEL COMPUTING 2013年第10期39卷 603-614页

作者： Saougkos, Dimitris Manis, George Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece

In this paper we suggest a new approach for solving the hyperplane problem, also known as "wavefront" computation. In direct contrast to most approaches that reduce the problem to an integer programming one or use several heuristic approaches, we gather information at compile time and delegate the solution to run time. We present an adaptive technique which intuitively calculates which new threads will be able to be executed in the next computation cycle based on which threads are executed in the current one. Moving the solution to the run time environment provides us with higher versatility alongside a perfect solution of the underlying hyperplane pattern being discovered without the need to perform any prior calculations. The main contribution of this paper is the presentation of the self adaptive algorithm, an algorithm which does not need to know the tile size (which controls the granularity of parallelism) beforehand. Instead, the algorithm itself adapts the tile size while the program is running in order to achieve optimal efficiency. Experimental results show that if we have a sufficient number of parallel processing elements to diffuse the scheduler's workload, its overhead becomes low enough that it is overshadowed by the net gain in parallelism. For the implementation of the algorithm we suggest, and for our experimentations our parallelizing compiler C2 mu TC/SL is used, a C parallelizing compiler which maps sequential programs on the SVP processor and model. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Self-adaptive Run-time scheduling parallelizing compiler Multithreaded processing

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A novel compiler support for automatic parallelization on multicore systems

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PARALLEL COMPUTING 2013年第9期39卷 442-460页

作者： Andion, Jose M. Arenaz, Manuel Rodriguez, Gabriel Tourino, Juan Univ A Coruna Dept Elect & Syst La Coruna 15071 Spain

The widespread use of multicore processors is not a consequence of significant advances in parallel programming. In contrast, multicore processors arise due to the complexity of building power-efficient, high-clock-rate, single-core chips. Automatic parallelization of sequential applications is the ideal solution for making parallel programming as easy as writing programs for sequential computers. However, automatic parallelization remains a grand challenge due to its need for complex program analysis and the existence of unknowns during compilation. This paper proposes a new method for converting a sequential application into a parallel counterpart that can be executed on current multicore processors. It hinges on an intermediate representation based on the concept of domain-independent kernel (e.g., assignment, reduction, recurrence). Such kernel-centric view hides the complexity of the implementation details, enabling the construction of the parallel version even when the source code of the sequential application contains different syntactic variations of the computations (e.g., pointers, arrays, complex control flows). Experiments that evaluate the effectiveness and performance of our approach with respect to state-of-the-art compilers are also presented. The benchmark suite consists of synthetic codes that represent common domain-independent kernels, dense/sparse linear algebra and image processing routines, and full-scale applications from SPEC CPU2000. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Automatic parallelization parallelizing compiler Source-to-source compiler compiler intermediate representation Domain-independent kernel Multicore processor

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Communication-free data alignment for arrays with exponential references in parallelizing compilers for scalable parallel systems

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JOURNAL OF SUPERCOMPUTING 2012年第1期60卷 4-30页

作者： Guo, Minyi Chang, Weng-Long Jiang, Bo Huang, Shu-Chien Tsai, Sien-Tang Ho, Michael (Shan-Hui) Dalian Maritime Univ Sch Informat Engn Dalian 116026 Liaoning Peoples R China Natl Kaohsiung Univ Appl Sci Dept Comp Sci & Informat Engn Kaohsiung 807 Taiwan Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Fukushima 9658580 Japan Natl PingTung Univ Educ Dept Comp Sci Pingtung Taiwan So Taiwan Univ Technol Dept Informat Management Tainan 710 Taiwan Ming Chuan Univ Sch Informat Technol Dept Informat Management Tao Yuan 333 Taiwan

In loops, some arrays are referenced with induction variables. To parallelize such kind of loops, those induction variables should be substituted. Thus, those array references that were substituted are formulated as nonlinear expressions. The goal of data alignment is to intelligently map the computations and data onto a set of virtual processors which are organized as a Cartesian grid (or a template in HPF terms), and to provide data locality for parallelizing compilers so that data access communication costs can be minimized. Most data alignment methods are mainly devised to align the referenced arrays using linear subscripts or quadratic subscripts with n loop index variables, and the methods are well developed. Seldom work, however, is researched on the nonlinear expressions of index variables. This paper proposes a new communication-free data alignment technique to align the referenced arrays using exponential subscripts with n loop index variables or other complex nonlinear expressions. The experimental results using SPEC95FP Benchmarks point out that the techniques proposed in the paper can improve the execution time of the subroutines in these benchmarks.

关键词： parallelizing compiler Communication-free alignment Communication optimization Loop optimization Data dependence analysis Load balancing

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Transitive Closure of a Union of Dependence Relations for Parameterized Perfectly-Nested Loops

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12th International Conference on Parallel Computing Technologies (PaCT)

作者： Bielecki, Wlodzimierz Kraska, Krzysztof Klimek, Tomasz West Pomeranian Univ Technol Fac Comp Sci & Informat Technol PL-71210 Szczecin Poland

ISBN: (纸本)9783642399572;9783642399589

This paper presents a new approach for computing the transitive closure of a union of relations describing all the dependences in both uniform and quasi-uniform perfectly-nested parameterized loops. This approach is based on calculating the basis of a dependence distance vectors set. The procedure has polynomial time complexity for most steps of calculations. This allows us to effectively extract both fine-and coarse-grained parallelism in loops using techniques based on applying the transitive closure of dependence relations. The effectiveness and time complexity of the approach are evaluated for loops provided by the NAS Parallel Benchmark Suite.

关键词： transitive closure parameterized dependence perfectly-nested loop parallelizing compiler

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