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CODE TRANSFORMATIONS FOR ENHANCING THE PERFORMANCE OF SPECULATIVELY PARALLEL THREADS

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2012年第2期21卷 1240008-1-1240008-23页

作者： Wang, Shengyue Yew, Pen-Chung Zhai, Antonia Univ Minnesota Dept Comp Sci & Engn Minneapolis MN 55455 USA Oracle Corp Santa Clara CA 95054 USA

As technology advances, microprocessors that integrate multiple cores on a single chip are becoming increasingly common. How to use these processors to improve the performance of a single program has been a challenge. For general-purpose applications, it is especially difficult to create efficient parallel execution due to the complex control flow and ambiguous data dependences. Thread-level speculation and transactional memory provide two hardware mechanisms that are able to optimistically parallelize potentially dependent threads. However, a compiler that performs detailed performance trade-off analysis is essential for generating efficient parallel programs for these hardwares. This compiler must be able to take into consideration the cost of intra-thread as well as inter-thread value communication. On the other hand, the ubiquitous existence of complex, input-dependent control flow and data dependence patterns in general-purpose applications makes it impossible to have one technique optimize all program patterns. In this paper, we propose three optimization techniques to improve the thread performance: (i) scheduling instruction and generating recovery code to reduce the critical forwarding path introduced by synchronizing memory resident values;(ii) identifying reduction variables and transforming the code the minimize the serializing execution;and (iii) dynamically merging consecutive iterations of a loop to avoid stalls due to unbalanced workload. Detailed evaluation of the proposed mechanism shows that each optimization technique improves a subset but none improve all of the SPEC2000 benchmarks. On average, the proposed optimizations improve the performance by 7% for the set of the SPEC2000 benchmarks that have already been optimized for register-resident value communication.

关键词： Thread-level speculation multicore systems compiler optimizations parallelizing compiler

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A Nested Loop Fusion Algorithm Based on Cost Analysis

A Nested Loop Fusion Algorithm Based on Cost Analysis

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14th IEEE International Conference on High Performance Computing and Communications (HPCC) / IEEE 9th International Conference on Embedded Software and Systems (ICESS)

作者： Zhao Jie Zhao Rongcai Yao Yuan China Natl Digital Switching Syst Engn & Technol Zhengzhou 450002 Henan Peoples R China

ISBN: (纸本)9780769547497

When applying Loop Fusion technology in the existing parallelizing compiler systems, the combined loop may not gain better parallel efficiency due to the lack of the consideration to the cost analysis of parallel loops. By improving the execution process of parallelizing compiler systems, we proposed a nested loop fusion algorithm based on cost analysis. It can not only optimize the execution process of parallelizing compiler system but also ensure that the combined loop having been applied Loop Fusion technology can get positive speedup. We implemented this algorithm on a specific parallelizing compiler and compiled some benchmark programs by the compiler. The experimental results show that the efficiency of the parallel programs increases by 5% to 20%.

关键词： parallelizing compiler loop fusion cost analysis nested loop

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Mapping Multi-Domain Applications onto Coarse-Grained Reconfigurable Architectures

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第5期30卷 637-650页

作者： Lee, Ganghee Choi, Kiyoung Dutt, Nikil D. Samsung Elect Co SoC Platform Dev Team System LSI Div Gyeonggi 445701 South Korea Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151600 South Korea Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif Irvine Dept Elect Engn Irvine CA 92697 USA

Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their performance and flexibility. However, their applications have been restricted to domains based on integer arithmetic since typical CGRAs support only integer arithmetic or logical operations. This paper introduces approaches to mapping applications onto CGRAs supporting both integer and floating-point arithmetic. After presenting an optimal formulation using integer linear programming, we present a fast heuristic mapping algorithm. Our experiments on randomly generated examples generate optimal mapping results using our heuristic algorithm for 97% of the examples within a few seconds. We observe similar results for practical examples from multimedia and 3-D graphics benchmarks. The applications mapped on a CGRA show up to 120 times performance improvement compared to software implementations, demonstrating the potential for application acceleration on CGRAs supporting floating-point operations.

关键词： Design automation high-level synthesis parallelizing compiler reconfigurable architecture

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OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

OSCAR API for Real-Time Low-Power Multicores and Its Perform...

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22nd International Workshop on Languages and compilers for Parallel Computing

作者： Kimura, Keiji Mase, Masayoshi Mikami, Hiroki Miyamoto, Takamichi Shirako, Jun Kasahara, Hironori Waseda Univ Dept Comp Sci & Engn Shinjuku Ku Tokyo Japan

ISBN: (纸本)9783642133732

OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory;data transfer using a DMA controller;and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR, compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR. API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API achie

关键词： Multicore API parallelizing compiler Power Reduction

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compiler Optimizations for parallelizing General-Purpose Applications under Thread-Level Speculation 08

Compiler Optimizations for Parallelizing General-Purpose App...

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ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 08)

作者： Zhai, Antonia Wang, Shengyue Yew, Pen-Chung He, Guojin Univ Minnesota Dept Comp Sci & Engn Minneapolis MN 55455 USA

No abstract available.

ISBN: (纸本)9781595939609

No abstract available.

关键词： Thread-Level Speculation Multicore systems compiler Optimizations parallelizing compiler

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Power-aware compiler controllable chip multiprocessor

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IEICE TRANSACTIONS ON ELECTRONICS 2008年第4期E91C卷 432-439页

作者： Shikano, Hiroaki Shirako, Jun Wada, Yasutaka Kimura, Keiji Kasahara, Hironori Waseda Univ Dept Comp Sci Tokyo 1698555 Japan Hitachi Ltd Cent Res Lab Kokubunji Tokyo 1858601 Japan

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

关键词： chip multiprocessor parallelizing compiler frequency and voltage control

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The Control, Communication, and Computation Language (C3L): Completing the Design Cycle in Complex Distributed System Development

The Control, Communication, and Computation Language (C3L): ...

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作者： Sustersic, John Phillip PennState University Libraries

学位级别：Doctor of Philosophy

Innovations in computing and communications have enabled autonomous electromechanical devices that change their internal states in response to real-time interactions with other devices, software agents, or smart sensors. Ad-hoc wireless networks of such devices may be engineered to perform autonomous missions like battlefield surveillance using sensor networks or multi-robot air campaigns. A critical research challenge is to harness the capabilities of these devices via ad-hoc wireless networks to invoke deliberate processes in response to operational dynamics and perform collaborative missions effectively. The Control, Communication and Computation Language (C3L) is a language designed to capture the semantics of the dynamic architectures of such distributed systems and concisely express complex, time-critical and mission-critical operations within the system. The alphabet of C3L consists of atomic events and actions that may be either controllable or uncontrollable. Atomic events and actions are combined in various ways to represent composite behaviors as event/action sequences. This programming paradigm enables heterogeneous, independently-developed devices plug-n-play compatibility in ad-hoc networked applications with either independent or coordinated strategies. By embedding the operational dynamics of the system in the higher-level semantics of the language, this framework permits multi-level fusion of distributed data in an intuitive manner. The revised syntax and a complete operational semantic description of C3L are presented and detailed. To more fully explore the value of C3L as a tool for rapid development and testing of scalable distributed programs for autonomous devices, a C3L compiler has been developed for the language. The compiler exploits the implicit task-level parallelism inherent in C3L programs to automatically generate multi-threaded executable programs. Based on the Microsoft Phoenix framework for compiler development and optimization, the

关键词： parallelizing compiler Distributed Systems Programming Formal Semantics Embedded Systems Computer Languages Mine Counter Measures

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Scheduling contention-free irregular redistributions in parallelizing compilers

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JOURNAL OF SUPERCOMPUTING 2007年第3期40卷 229-247页

作者： Hsu, Ching-Hsien Chen, Shih-Chang Lan, Chao-Yang Chung Hua Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan

Irregular array redistribution has been paid attention recently since it can distribute different size of data segment to heterogeneous processors according to their computational ability. It's also the reason why it has been kept an eye on load balance. High Performance Fortran Version 2 (HPF2) provides GEN-BLOCK distribution format which facilitates generalized block distributions. In this paper, we present a two-phase degree-reduction (TPDR) method for scheduling HPF2 irregular array redistribution. Using a bipartite communication graph, the first phase of TPDR schedules communication links adjacent to processors that with degree greater than two. A communication step will be scheduled follow each degree- reduction iteration. The second phase of TPDR schedules remaining messages of all processors that with degree-2 and degree-1 using an adjustable coloring mechanism. Ali extended algorithm based on TPDR is also presented itt this paper. Effectiveness of the proposed methods not only avoids node contention but also shortens the overall communication cost. The proposed methods are also practicable due to low algorithmic complexity. To evaluate the performance of our methods, we have implemented both algorithms along with the divide-and-conquer algorithm and two scheduling mechanism. The simulation results show improvement of total communication costs.

关键词： irregular redistribution communication scheduling GEN_BLOCK degree-reduction parallelizing compiler

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Communication optimization on automatic program parallelization

Communication optimization on automatic program parallelizat...

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8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing/3rd ACIS International Workshop on Self-Assembling Wireless Networks

作者： Dong Chun-Li Zhao Rong-Cai Ma Zhuo-Jie Li Dong-Hong Natl Digital Switching Syst Engn & Technol Res Ct Zhengzhou 450002 Peoples R China

ISBN: (纸本)9780769529097

Minimizing communication by increasing the locality of data references is an important optimization for achieving high performance on distributed memory machines. But in the progress of decomposition, reorganization is inevitable. And the communication produced by reorganization is inevitable too. In this paper, the authors present a linear decomposition algorithm that automatically finding computation and data decomposition, including finding data and computations decomposition that has data reorganization communication. And the authors improve the method and reduce the communication cost by merging parallel regions with the same data decomposition.

关键词： parallelizing compiler MPI data reorganization parallel region merging data decomposition computation decomposition

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Design and implementation of the loop restructuring feature for the MIRAI parallelizing compiler

Design and implementation of the loop restructuring feature ...

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International Conference on Parallel and Distributed Processing Techniques and Applications

作者： Nobuhara, H Mineo, M Uehara, T Saito, S Kunieda, Y Wakayama Univ Wakayama Japan

ISBN: (纸本)1892512459

When loops in sequential programs written in procedural programming languages are parallelized, automatic parallelizing compilers should perform data dependence analysis in order to preserve constraints by data reference order. Although loops with dependences as determined by a dependence analyzer cannot be parallelized as-is, in general, some can be parallelized after applying appropriate loop restructuring optimizations. This paper deals with the design and implementation of the loop restructuring feature of our automatic parallelizing compiler, MIRAL And also it shows the evaluation results of several pilot studies by hand-compiling some test programs.

关键词： loop restructuring loop transformation optimization parallelization parallelizing compiler

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