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Predecessor/successor approach for high-performance run-time wavefront scheduling

INFORMATION SCIENCES 2006年第7期176卷 845-860页

作者： Huang, TC Hsu, PH Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 804 Taiwan Cheng Shiu Inst Technol Dept Elect Engn Kaohsiung 833 Taiwan

Most scientific applications rely on parallel Multiprocessor computing to enhance Performance. However, the irregular loops within these applications obstruct the parallefism analysis at compile-time. Rauchwerger et al. presented a run-time method to extract the hidden parallelism in a program using dependence chains. The relative overhead degrades this approach's performance due to the mass storage requirement and huge array reference processing. In this Study, a new predecessor/successor approach is developed in which high-level predecessor/successor information is recorded and processed efficiently. A predecessor/successor table is constructed first in the inspector phase so that only the successor iterations in the current wavefront need to be examined, instead of the entire loop iterations during wavefront scheduling. Usually, the performance of dependence chain approach degrades dramatically for a hot-spot access pattern, but Our scheme works very efficiently in this case. The experimental results using synthetic code and real programs are presented to prove the superiority of the proposed approach. (c) 2005 Elsevier Inc. All rights reserved.

关键词： parallelizing compiler dependence chain loop parallelization inspector/executor wavefront scheduling

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Revisiting communication code generation algorithms for message-passing systems

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INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS 2006年第5期21卷 323-344页

作者： Ferner, Clayton Univ N Carolina Dept Comp Sci 601 S Coll Rd Wilmington NC 28403 USA

In this paper, we investigate algorithms for generating communication code to run on distributed-memory systems. We modify algorithms from previously published work and prove that the algorithms produce correct code. We then extend these algorithms to incorporate the mapping of virtual to physical processors and prove the correctness of this extension. This technique can reduce the number of interprocessor messages. In the examples that we show, the total number of messages was reduced from O(N-2) to O(P-2), where N is the input size and P is the number of physical processors. The reason that it is important to revisit communication code generation and to introduce a formal specification of the incorporation of mapping in the communication code generation is so that we can make use of the many scheduling heuristics proposed in the literature. We need a generalized mapping function so that we can apply different mapping and scheduling heuristics proposed in the literature for each input program, therefore improving the average performance.

关键词： parallelizing compiler Parallel computation Distributed-memory Message-passing Mapping Code generation

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An overlapping task assignment scheme for hierarchical coarse-grain task parallel processing

An overlapping task assignment scheme for hierarchical coars...

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10th International Workshop on compilers for Parallel Computers (CPC 2003)

作者： Yoshida, Akimasa Toho Univ Dept Informat Sci Chiba 2748510 Japan

This paper proposes an overlapping task assignment scheme for the hierarchical coarse-grain task parallel processing on multiprocessor systems. In coarse-grain task parallel processing, the compiler extracts parallelism among coarse-grain tasks automatically and the coarse-grain tasks are assigned to processor clusters at runtime. However, several programs may decrease the processor-cluster utilization factor owing to lack of parallelism inside each coarse-grain task. Therefore, in order to improve the processor-cluster utilization factor, this paper proposes the execution scheme with overlapping task assignment whose dynamic scheduler can assign several coarse-grain tasks to a processor cluster simultaneously. Also, the performance evaluations by simulations and executions on SMP showed that the proposed scheme could reduce the execution time remarkably. Copyright (c) 2006 John Wiley & Sons, Ltd.

关键词： parallelizing compiler coarse-grain parallelism dynamic scheduling SMP overlapping assignment task graph

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Development and implementation of an interactive parallelization assistance tool for OpenMP: iPat/OMP

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2006年第2期E89D卷 399-407页

作者： Ishirara, M Honda, H Sato, M Univ Electrocommun Grad Sch Informat Syst Chofu Tokyo 1828585 Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki 3058577 Japan

iPat/OMP is an interactive parallelization assistance tool for OpenMP. In the present paper, we describe the design concept of iPat/OMP, the parallelization sequence achieved by the tool and its current implementation status. In addition, we present an evaluation of the performance of the implemented functionalities. The experimental results show that iPat/OMP can detect parallelism and create an appropriate OpenMP directive for several for-loops.

关键词： OpenMP interactive parallelization assistance tool parallelizing compiler human readability

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An overlapping task assignment scheme for hierarchical coarse-grain task parallel processing

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2006年第11期18卷 1335-1351页

作者： Yoshida, Akimasa Toho Univ Dept Informat Sci Chiba 2748510 Japan

关键词： parallelizing compiler coarse-grain parallelism dynamic scheduling SMP overlapping assignment task graph

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Language and compiler design for streaming applications

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2005年第2-3期33卷 261-278页

作者： Amarasinghe, S Gordon, MI Karczmarek, M Lin, J Maze, D Rabbah, RM Thies, W MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

High-performance streaming applications are a new and distinct domain of programs that is increasingly important. The StreamIt language provides novel high-level representations to improve programmer productivity and program robustness within the streaming domain. At the same time, the StreamIt compiler aims to improve the performance of streaming applications via stream-specific analysis and optimizations. In this paper, we motivate, describes and justify the StreamIt language which include a structured model of streams, a messaging system for control, and a natural textual syntax.

关键词： stream computing StreamIt parallelizing compiler tiled-processor architectures productivity

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Experiments with auto-parallelizing SPEC2000FP benchmarks

Experiments with auto-parallelizing SPEC2000FP benchmarks

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17th International Workshop on Languages and compilers for High Performance Computing

作者： Zhang, GS Unnikrishnan, P Ren, J IBM Corp Toronto Lab Toronto ON L6G 1C7 Canada

ISBN: (纸本)354028009X

In this paper, we document the experimental work in our attempts to automatically parallelize SPEC2000FP benchmarks for SNIP machines, This is not purely a research project. It was implemented within IBM's software laboratory in a commercial compiler infrastructure that implements OpenMP 2.0 specifications in both Fortran and C/C++. From the beginning, our emphasis is on using simple parallelization techniques. We aim to maintain a good trade-off between performance, especially scalability of an application program and its compilation time. Although the parallelization results show relatively low speed up, it is still promising considering the problems associated with explicit parallel programming and the fact that more and more multi-thread and multi-core chips will soon be available even for home computing.

关键词： automatic parallelization parallelizing compiler SMT machine OpenMP parallel do

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An efficient algorithm for communication set generation of data parallel programs with block-cyclic distribution

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PARALLEL COMPUTING 2004年第4期30卷 473-501页

作者： Hwang, GH Natl Taiwan Normal Univ Dept Informat & Comp Educ Taipei Taiwan

Data parallel programming languages, such as High Performance Fortran, are widely regarded as a promising means for writing portable programs for distributed-memory machines. In this paper, we present a new algorithm for computing the communication sets in array section movements with block-cyclic (cyclic (k) in HPF) distribution. Our framework can handle multi-level alignments, multi-dimensional arrays, array intrinsic functions, affine indices and axis exchanges in the array subscript. Instead of employing the linear diophantine equation solver, a new algorithm which does not rely on the linear diophantine equation solver to calculate communication sets is proposed. We use formal proof and experimental results to show that it is more efficient than previous solutions to the same problem. Another important contribution of this paper is that we prove that the compiler is able to compute efficiently the communication sets of block-cyclic distribution as long as the block sizes of the arrays are set to be identical or the lowest common multiple (LCM) of block sizes is not a huge integer. We demonstrate it by thorough complexity analyses and extensive experimental results. (C) 2004 Elsevier B.V. All rights reserved.

关键词： HPF compiler distributed memory machines parallelizing compiler data parallel programs block-cyclic distributions

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A new practical array data dependence analysis for parallelizing compilers

A new practical array data dependence analysis for paralleli...

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International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems

作者： Mineo, M Uehara, T Saito, S Kunieda, Y Wakayama Univ Fac Syst Engn Grad Sch Wakayama 6408510 Japan

ISBN: (纸本)0769520197

Data dependence analysis is essential for automatic parallelizing compilers. compilers determine the possibility of parallelization on given source programs by using the result from data dependence analysis. Several dependence analysis tests on array data have been already proposed. Each test cannot avoid the trade-off between its analysis speed and exactness of analysis. Among such tests, the Omega test is well known as an exact test for the broader class of index expressions. However, the Omega test algorithm is so complicated that its analysis is very time consuming and it is difficult to implement the Omega test. Therefore, in this paper a new original test is proposed, whose algorithm combines both the Simplex method for linear programming and an exhaustive solution search method. The algorithm, its implementation details, and evaluation applied to concrete numerical programs are also described.

关键词： data dependence dependence analysis linear programming parallelization parallelizing compiler

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A statement based parallelizing framework for processor-in-memory architectures

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INFORMATION PROCESSING LETTERS 2003年第3期85卷 159-163页

作者： Huang, TC Chu, SL Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung Taiwan

It is widely known that current memory architecture is one of the bottlenecksfor high-performance computers due to the increasing gap between the processor speed and memorylatency. For this reason, several architectures, called intelligent memory (IRAM) orprocessor-in-memory (PIM), have been studied in recent years aiming to integrate the processor andmemory together. A merit of PIM architecture is that the PIM chips can be used to replace the mainmemory chips in a workstation and act as coprocessors when main processor spawns them. This approachhas been adopted by Active Page, DIVA, and FlexRAM, among others. This class of architecturesprovides a hierarchical hybrid multiprocessor environment: host (main) processors and memoryprocessors. Host processor is more powerful with a deep cache hierarchies and higher latency toaccess memory. By contrast, memory processors are usually less powerful but with a lower latency inmemory access. The major problems we address in this paper are: how to dispatch suitable tasks tothese different processors in PIM by their computing power and characteristics to reduce their idletime, and how to partition the original program then execute simultaneously on these heterogeneousprocessors mixture. Based on our earlier work, we propose the SAGE(Statement-Analysis-Grouping-Evaluation) system to analyze the source program, generate a WeightPartition Dependence Graph (WPG), determine the weight of each block, and then dispatch the mostsuitable jobs to the host and memory processors, respectively. From the experiment, we find thatquite good speedup is obtained, which even exceeds the computation capability ratio in 1-host and1-memory processors environment.

关键词： processor-in-memory statement analysis SAGE parallelizing compiler FlexRAM scheduling

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