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Optimization design of a full asynchronous pipeline circuit based on null convention logic

Journal of Semiconductors 2009年第7期30卷 125-130页

作者：管旭光周端杨银堂 Institute of Microelectronics Xidian University

This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous *** combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing *** complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic *** penalty brought by null cycle is reduced while the data processing capacity is *** novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS *** on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power *** indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.

关键词： threshold gate asynchronous circuit self-timed circuit high-speed asynchronous pipeline parallelprocessing

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AN EFFICIENT PARALLEL PROCESSING OPTIMAL CONTROL SCHEME FOR A CLASS OF NONLINEAR COMPOSITE SYSTEMS

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Acta Mathematica Scientia 2017年第3期37卷 703-721页

作者： A. JAJARMT M. HAJIPOUR Department of Electrical Engineering University of Bojnord P.O. Box 94531-1339 Bojnord Iran Department of Mathematics Faculty of Basic Sciences Sahand University of Technology P.O. Box 51335-1996 Tabriz Iran

This article presents an efficient parallel processing approach for solving the opti- mal control problem of nonlinear composite systems. In this approach, the original high-order coupled nonlinear two-point boundary value problem （TPBVP） derived from the Pontrya- gin＇s maximum principle is first transformed into a sequence of lower-order deeoupled linear time-invariant TPBVPs. Then, an optimal control law which consists of both feedback and forward terms is achieved by using the modal series method for the derived sequence. The feedback term specified by local states of each subsystem is determined by solving a ma- trix Riccati differential equation. The forward term for each subsystem derived from its local information is an infinite sum of adjoint vectors. The convergence analysis and parallel processing capability of the proposed approach are also provided. To achieve an accurate feedforward-feedbaek suboptimal control, we apply a fast iterative algorithm with low com- putational effort. Finally, some comparative results are included to illustrate the effectiveness of the proposed approach.

关键词： Modal series method nonlinear composite system optimal control parallelprocessing

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Design of array processors for 2-D Discrete Fourier Transform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1997年第4期E80D卷 455-465页

作者： Peng, ST Sedukhin, I Sedukhin, S Department of Computer Software Distributed Parallel Processing Laboratory University of Aizu Aizu-Wakamatsu-shi. 965 -80 Japan RandD Group Hiwada Electronic Corporation (Pioneer Group) Fukushima-ken 969-13 Japan

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

关键词： algorithm mapping 2-dimensional discrete Fourier transform parallelprocessing systolic array processors VLSI architectures

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IMPROVING PERFORMANCE AND PRODUCTIVITY FOR SOFTWARE DEVELOPMENT ON TI MULTICORE DSP PLATFORMS 6

IMPROVING PERFORMANCE AND PRODUCTIVITY FOR SOFTWARE DEVELOPM...

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6th European Embedded Design in Education and Research Conference (EDERC)

作者： Aguilar, Miguel Jimenez, Ronny Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst D-52056 Aachen Germany

ISBN: (纸本)9781479968435

Complexity of modern applications, the performance requirements and the power constraints are the major driving forces that motivate the use of Multiprocessor Systems on Chip (MPSoCs). Programming these platforms is still a big challenge, posing a multitude of software design issues: What is the right MPSoC programming model to capture parallelism?, How to parallelize legacy C code?, How to achieve optimal utilization of processing elements?, How to minimize communication overhead?, How to explore the vast software mapping design space?. Traditional compiler technology does not solve these challenges, as it does not consider the architectural characteristics introduced by MPSoCs. Several research efforts have been directed to address these challenges. One example is the MAPS framework (MPSoC Application Programming Studio) that offers facilities for programming heterogeneous and homogeneous MPSoCs. In this paper, we focus on the applicability of this tool to the software development on the TI Keystone Multicore DSP platforms. The analysis considers both performance and productivity improvements achieved by MAPS.

关键词： Benchmarktesting Digitalsignalprocessing Manuals Multicoreprocessing parallelprocessing Productivity Transformcoding Software design computer software productivity Platform maps Multi-core processors Digital signal processing Desmoplakin Gene Titanium Thallium Programming parallelism

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Determination of the Track Parallelism of a Sandwich Panel Producing Machine 12

Determination of the Track Parallelism of a Sandwich Panel P...

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12th IEEE International Symposium on Intelligent Systems and Informatics (SISY)

作者： Hermann, Gyula Obuda Univ Budapest Hungary

ISBN: (纸本)9781479959969

Beside the dimensions, the geometric quality of a sandwich panel is determined by the straightness and the parallelism of the edges of the panel. This in turn is highly influenced by the guide ways. The paper describes the principle and the construction of an instrument for determining the straightness and the relative parallelism of the guide ways of a sandwich panel producing machine.

关键词： Instruments Measurementbylaserbeam Measurementuncertainty parallelprocessing Rails Sensors Uncertainty Rail Railway Rail parallelism Sandwich panels Sensors Device Panel Synclitism Sandwiches flatness Uncertainty machine Caste determination Sex Determination Processes

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GOP LEVEL PARALLELISM IMPLEMENTATION FOR REAL-TIME H264/AVC VIDEO ENCODER ON MULTICORE DSP TMS320C6472 6

GOP LEVEL PARALLELISM IMPLEMENTATION FOR REAL-TIME H264/AVC ...

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6th European Embedded Design in Education and Research Conference (EDERC)

作者： Bahri, Nejmeddine Grandpierre, Thierry Ben Ayed, Med Ali Masmoudi, Nouri Akil, Mohamed Univ Paris EST LIGM Lab ESIEE Engn Paris France Univ Sfax LETI Lab Natl Sch Engineers Sfax Tunisia

ISBN: (纸本)9781479968435

In this paper, we exploit the parallelism offered by six-core Digital Signal Processor (DSP) TMS320C6472 to implement the H264/AVC video encoder in order to meet the real-time constraint for different video resolutions. To enhance the encoding speed, GOP Level Parallelism approach is implemented on 5 slave DSP cores. A master core is reserved to manage data transfers among DSP memory and personal computer in order to perform a real-time video encoding demo taken into account video capture and bit-stream storage. Multithreading algorithm and ping-pong buffers technique are used in order to optimize the communication overhead. Experimental results show that our enhanced implementation allows to overcome the real-time constraint by reaching up to 120 f/s (frame/second) for Common Intermediate Format resolution (CIF 352x288) and 35f/s for Standard Definition (SD 720x480). Our proposed approach can save about 80% of run-time for High Definition resolution (HD 1280x720). The Enhanced GOP Level parallelism approach on five DSP cores achieves a good average speedup factor of 4.88 without inducing any quality degradation or bit-rate increment.

关键词： Digitalsignalprocessing Encoding Multicoreprocessing parallelprocessing Real-timesystems Streamingmedia Videocoding

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PREESM: A DATAFLOW-BASED RAPID PROTOTYPING FRAMEWORK FOR SIMPLIFYING MULTICORE DSP PROGRAMMING 6

PREESM: A DATAFLOW-BASED RAPID PROTOTYPING FRAMEWORK FOR SIM...

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6th European Embedded Design in Education and Research Conference (EDERC)

作者： Pelcat, Maxime Desnos, Karol Heulot, Julien Guy, Clement Nezan, Jean-Francois Aridhi, Slaheddine INSA Rennes IETR UMR CNRS 6164 F-35708 Rennes France Texas Instruments France Cagnes Sur Mer France

ISBN: (纸本)9781479968435

The high performance Digital Signal Processors (DSPs) currently manufactured by Texas Instruments are heterogeneous multiprocessor architectures. Programming these architectures is a complex task often reserved to specialized engineers because the bottlenecks of both the algorithm and the architecture need to be deeply understood in order to obtain a fairly parallel execution. The PREESM framework objective is to simplify the programming of multicore DSP systems by building on dataflow programming methods. The current functionalities of this scalable framework cover memory and time analysis, as well as automatic deadlock-free code generation. Several tutorials are provided with the tool for fast initiation of C programmers to multicore DSP programming. This paper demonstrates PREESM capabilities by comparing simulation and execution performances on a stereo matching algorithm prototyped on the TMS320C6678 8-core DSP device.

关键词： Algorithmdesignandanalysis Computationalmodeling Digitalsignalprocessing Multicoreprocessing parallelprocessing Throughput Throughput Programming Digital signal processing Desmoplakin Gene MULTIPROCESSOR ARCHITECTURE Multi-core processors ARCHITECTURE Building construction Code generation Traffic Bottlenecks Frameworks

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A Hierarchical Architecture Description for Flexible Multicore System Simulation 12

A Hierarchical Architecture Description for Flexible Multico...

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12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)

作者： Bruckschloegl, Thomas Oey, Oliver Rueckauer, Michael Stripf, Timo Becker, Juergen Karlsruhe Inst Technol Inst Informat Proc Technol ITIV D-76021 Karlsruhe Germany

ISBN: (纸本)9781479942930

As processors and systems on chip in the embedded world increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using high level programming languages, like Scilab or MATLAB. The ALMA toolset solves this problem: it takes Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimizations. The platform information is provided by an architecture description language designed for the purpose of a flexible system description as well as simulation. A hierarchical system description in combination with a parameterizable simulation environment allows fine-grained trade-offs between simulation performance and simulation accuracy.

关键词： Accuracy Multicoreprocessing Optimization parallelprocessing Programprocessors System-on-chip system-on-chip Architecture description languages PROCESSOR multiprocessor system on chip ARCHITECTURE Multi-core processors systems simulation Parallel programming Simulated Environment Building construction FLEXIBLE

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OpenCL Application Auto-Tuning and Run-Time Resource Management for Multi-Core Platforms 12

OpenCL Application Auto-Tuning and Run-Time Resource Managem...

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12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)

作者： Gadioli, Davide Libutti, Simone Massari, Giuseppe Paone, Edoardo Scandale, Michele Bellasi, Patrick Palermo, Gianluca Zaccaria, Vittorio Agosta, Giovanni Fornaciari, William Silvano, Cristina Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781479942930

To support adaptivity of data parallel applications on multi-core platforms, we propose a framework based on the combination of OpenCL application auto-tuning and run-time resource management. The framework addresses computationally intensive multimedia OpenCL applications. For these target applications, we show that application auto-tuning, based on design-time analysis, can become synergistic with run-time resource management. In the proposed framework, run-time decisions are taken by each application, autonomously, to achieve system adaptivity. This paper describes the methodology and related toolchain, defined during the 2PARMA European project, based on the integration of independent tools to provide effective compilation of OpenCL code, multi-objective design space exploration, application monitoring and tuning and system-wide run-time resource management. Experimental results are reported for design optimization of an OpenCL stereo-matching application and then for a resource contention scenario where multiple stereo-matching applications are executed on the same platform with different run-time requirements.

关键词： Monitoring Optimization parallelprocessing Resourcemanagement Runtime Spaceexploration Throughput Runtime management of resources Throughput Self tuning time series analysis Platform

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A New Parallel-by-Cell Approach to Undistorted DataCompression Based on Cellular Automatonand Genetic Algorithm

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Journal of Computer Science & Technology 1999年第6期14卷 572-579页

作者：顾静帅典勋 StateKeyLaboratoryofIntelligenceTechnologyandSystemTsinghuaUniversity Beijing100084PR.China

In this paper, a new parallel-by-cell approach to the undistorteddata compression based on cellular automaton and genetic algorithm is *** local compression rules in a cellular automaton are obtained by using a geneticevolutionary algorithm. The correctness of the hyper-parallel compression, the timecomplexity, and the relevant symbolic dynamic behaviour are discussed. In comparison with other traditional sequential or small-scale parallel methods for undistorteddata compression, the proposed approach shows much higher real-time performance,better suitability and feasibility for the systolic hardware implementation.

关键词： data compression genetic algorithm cellular automaton parallelprocessing

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