In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area ...
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In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered 0.18 mu m CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory(1).
This paper presents a new kind of quasi-cyclic irregular repeat accumulate (IRA) codes based on circulant permutation matrices called QC-IRA-d codes. The presented QC-IRA-d codes have lower encoding complexity than tr...
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This paper presents a new kind of quasi-cyclic irregular repeat accumulate (IRA) codes based on circulant permutation matrices called QC-IRA-d codes. The presented QC-IRA-d codes have lower encoding complexity than traditional IRA codes and can be decoded in a partially parallel decoder like QC-LDPC codes. Simulation results show that QC-IRA-d codes have good error-correcting performance.
The excellent error correction performance of Low-Density Parity Check code has made it widely used in many modern communication systems, including space communication system. This paper describes a design and FPGA im...
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ISBN:
(纸本)9789811065712;9789811065705
The excellent error correction performance of Low-Density Parity Check code has made it widely used in many modern communication systems, including space communication system. This paper describes a design and FPGA implementation of a quasi-cyclic LDPC decoder based on Min-Sum Algorithm. The partiallyparallel design solves the contradiction between the consumption of hardware resource and decoding efficiency. The decoder achieves up to a BER of 10(-3) at 4 dB, and a throughput of 300 Mbps per iteration for a code length of 8176.
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