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Plug-and-Play Network Reconfiguration algorithms to Maintain Regularity and Low Network Reconfiguration Needs

IEEE CONTROL SYSTEMS LETTERS 2022年 6卷 3451-3456页

作者： Studli, Sonja Yan, Yamin Seron, Maria M. Middleton, Richard H. Univ Newcastle Sch Engn Callaghan NSW 2308 Australia Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China

In this letter we propose algorithms to connect and disconnect nodes to/from an existing graph, which are able to maintain the regularity of a graph while requiring minimal reconfiguration of the network. Further, simulations suggest that the algorithms maintain a minimum bound on the algebraic connectivity of the graph. These properties of the algorithms suit their use in plug-and-play networks.

关键词： Graph theory Thermal stability Stability analysis Multi-agent systems partitioning algorithms Laplace equations Information exchange Control of networks networked control systems

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A Shared-Memory Algorithm for Updating Tree-Based Properties of Large Dynamic Networks

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IEEE TRANSACTIONS ON BIG DATA 2022年第2期8卷 302-317页

作者： Srinivasan, Sriram Pollard, Samuel D. Norris, Boyana Das, Sajal K. Bhowmick, Sanjukta Univ Nebraska Omaha Dept Comp Sci Omaha NE 68182 USA Univ Oregon Dept Comp & Informat Sci Eugene OR 97403 USA Missouri Univ Sci & Technol Dept Comp Sci Rolla MO 65409 USA

This paper presents a network-based template for analyzing large-scale dynamic data. Specifically, we propose a novel shared-memory parallel algorithm for updating tree-based structures or properties, such as connected components (CC) and minimum spanning trees (MST), on dynamic networks. The underlying idea is to update the information in a rooted tree data structure that stores the edges of the network that are most relevant to the analysis. Extensive experiments on real-world and synthetic networks demonstrate that, with the exception of the inherently sequential component for creating the rooted tree, our proposed updatiing algorithm is scalable and, in most cases, also requires significantly less memory, energy, and time than recomputing-from-scratch algorithm. To the best of our knowledge, this is the first parallel algorithm for updating MST on weighted dynamic networks. The rooted-tree based framework that we propose in this paper can be extended for updating other weighted and unweighted tree-based properties such as single source shortest path and betweenness and closeness centrality.

关键词： Heuristic algorithms Data structures Parallel algorithms Image edge detection Big Data partitioning algorithms Maintenance engineering Dynamic networks minimum spanning tree connected components shared memory algorithms

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Size Constrained K-Means Clustering for Controlled Design Structure Matrix partitioning

Size Constrained K-Means Clustering for Controlled Design St...

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Annual IEEE Systems Conference

作者： Heekun Roh Lilly Etzenbach Alexia Oltramare Johannes Norheim Olivier L. De Weck Dept. of Aeronautics and Astronautics Massachusetts Institute of Technology Cambridge USA Dept. of Aeronautics and Astronautics Massachusetts Institute of Technology Tufts University Cambridge USA Dept. of Design Manufacturing and Engineering Management University of Strathclyde Glasgow UK

ISBN: (数字)9798331508180

ISBN: (纸本)9798331508197

In this paper, we propose a novel clustering algorithm for Design Structure Matrices (DSMs) with the goal of providing a balanced system partitioning. DSMs are one of the standard forms of modeling the dependency structure between system components. They naturally reveal the complexity of the system and often provide insights for organizational management. In particular, partitioning a DSM into multiple clusters is widely studied in the literature, as the cluster structure either gives rise to a natural work breakdown structure for the organization or highlights hidden dependencies between clusters. Often, such clustering methods work directly on DSMs by permuting rows and columns randomly, making scalability an issue due to the exponentially growing search space with respect to DSM size. In this paper, we propose an alternative approach to clustering a DSM in its spectral space using the k-means algorithm. The spectral space of a DSM is the low-dimensional eigenvector space of the Laplacian of the given matrix, which is invariant to the row-column permutation of the original DSM. Furthermore, we introduce an Integer Linear Programming (ILP) method to constrain the size of each cluster to balance the resulting partitions, which is often not achievable using the generic kmeans algorithm. The DSM from a medium-sized jet engine is used to demonstrate the method's balancing properties. Then synthetic DSMs are used to show the method's scalability which is compared to the generic simulated annealing clustering algorithm.

关键词： Laplace equations Electric breakdown Scalability Clustering methods Standards organizations Clustering algorithms Simulated annealing Organizations Integer linear programming partitioning algorithms

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PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2022年第11期30卷 1783-1793页

作者： Lin, Jai-Ming Zane, Liang-Chi Tsai, Min-Chia Chen, Yung-Chen Lin, Che-Li Tsai, Chen-Fa Natl Cheng Kung Univ Dept Elect Engn Tainan 701401 Taiwan Global Unichip Corp Dept Phys Design Serv Tainan 700019 Taiwan

Even though routability is of great concern to a recent global placement algorithm, there still exists a large room to improve it. To make legalization more easier and get a better placement, this article proposes an iterative approach to refine cell locations after global placement, where wirelength and routability are separately optimized in each iteration. It first moves cells to better locations to reduce wirelength. Unlike previous approaches, our approach guarantees that no wirelength will be increased so that the previous optimization result can be better maintained. Moreover, we propose a delicate procedure to move cells according to their gain values to reduce the largest wirelength. Next, the whitespace re-allocation approach is applied to redistribute whitespace over a chip to improve routability without changing relative locations of cells. To ensure that enough space will be allocated to the most routing congestion regions, we propose a sigmoid function to increase routing demands of regions according to their routing overflows and number of pins. The experimental results show that our methodology can obtain shorter wirelength and better routability in industrial designs when compared to other approach.

关键词： Routing Optimization Pins partitioning algorithms Very large scale integration Safety Runtime Placement post-optimization routability

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Product Recognition for Inventory Management Using Spatial partitioning in a Multi-Camera System

Product Recognition for Inventory Management Using Spatial P...

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IEEE International Conference on Consumer Electronics (ICCE)

作者： Viduranga Munasinghe Tae-Ho Lee Tae Sung Kim Jin-Sung Kim Hyuk-Jae Lee Department of Electrical and Computer Engineering Seoul National University Seoul South Korea Department of Electronic Engineering SunMoon University Asan South Korea

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Recent advancements in deep learning have significantly improved object detection capabilities. However, accurately recognizing objects in environments with complex occlusions remains a challenge. For instance, detecting densely packed items on shelves in unmanned stores presents difficulties even for the most cutting-edge deep-learning object detectors. To address this issue, we propose a deep learning-based inventory management system tailored for multi-camera unmanned stores. The proposed method utilizes a Voronoi diagram-based ground plane localization technique along with regions of interest (ROI) obtained by using image difference. A weighted voting algorithm is employed to ensure an accurate inventory check. This approach outperforms conventional ROI detection methods by 10.45% in terms of recognition accuracy.

关键词： Deep learning Location awareness Accuracy Event detection Object detection Inventory management partitioning algorithms Reliability Object recognition Optimization

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DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch

DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Parti...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Zhen Yu Jinhao Li Jiaming Xu Shan Huang Jiancai Ye Ningyi Xu Guohao Dai Shanghai Jiao Tong University Infinigence-AI

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Text-Attributed Graphs (TAGs) tasks involve both textual node information and graph topological structure. The top-k method, using Language Models (LMs) for text encoding and Graph Neural Networks (GNNs) for graph processing, offers the best accuracy while balancing memory and training time. However, challenges still exist: (1) Static sampling of k neighbors reduces performance. Using a fixed k can result in sampling too few or too many nodes, leading to a 3.2% accuracy loss across datasets. (2) Time-consuming processing for non-trainable nodes. After partitioning all nodes into with-gradient trainable and without-gradient non-trainable sets, the number of non-trainable nodes is ~9-10 x larger than trainable nodes, resulting in nearly 70% of the total time. (3) Time-consuming data movement. For processing non-trainable nodes, after the text strings are tokenized into tokens on the CPU side, the data movement from host memory to GPU takes 30%-40% of the time. In this paper, we propose DyLGNN, an efficient end-to-end LM-GNN fine-tuning framework through three innovations: (1) Heuristic Node partitioning. We propose an algorithm that dynamically and adaptively selects “important” nodes to participate in the training process for downstream tasks. Compared to the static top-k method, we reduce the training memory usage by 24.0%. (2) Low-Degree Sparse Attention. We point out that the embedding of low-degree nodes has minimal impact on the final results (e.g. ~1.5% accuracy loss), therefore, We perform sparse attention computation on low-degree nodes to further reduce the computation caused by “unimportant” nodes, achieving an average 1.27 x speedup. (3) Asynchronous Sub-batch Pipeline. Within the top-k framework, we analyze the time breakdown of the LM inference component. Leveraging our heuristic node partitioning, which effectively minimizes memory demands, we can asynchronously execute data movement and computation, thereby overlapping the time required for data moveme

关键词： Training Technological innovation Accuracy Heuristic algorithms Pipelines Memory management Graphics processing units Europe Graph neural networks partitioning algorithms

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A partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs

A Partitioning-Based CAD Flow for Interposer-Based Multi-Die...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Mahesh A. Iyer Andrew B. Kahng Jason Luu Bodhisatta Pramanik Kristofer Vorwerk Grace Zgheib Altera University of California San Diego La Jolla CA USA Intel Corporation

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Multi-die interposer-based FPGA architectures present several design challenges: (i) limited inter-die connectivity (interposer) resources and (ii) increased interposer delays compared to intra-die routing. Addressing these challenges is critical, as compared to intra-die routing, they directly impact the routability, routed wirelength (rWL) and maximum clock frequency (Fmax) of the design. In this paper, we present a partitioning-based CAD flow tailored for interposer-based multi-die FPGA architectures. Central to our approach is FPGAPart, the first open-source timing-driven netlist partitioner that can handle FPGA designs while addressing modern architectural constraints. We integrate FPGAPart with the open-source tool VTR 7.0. In particular, we use: (i) VTR 7.0's pre-packing solutions as clustering hints during partitioning and (ii) the FP-Growth algorithm [14] to detect frequently occurring patterns (instances) across multiple timing paths for clustering. Additionally, we introduce neighborhood influences-based cutting planes into the core ILP solver in FPGAPart, resulting in a ~38× ILP runtime speedup with < 1 % degradation in solution quality, compared to using no neighborhood influences. Compared to the default VTR 7.0, our flow achieves a geometric mean improvement of ~3% in rWL and ~3% in Fmax for a two-die configuration, with similar improvements across other configurations. Compared to hMETIS [17], METIS [18] and TritonPart [5], FPGAPart achieves improvements up to ~4% in rWL and ~7 % in Fmax for a two-die configuration, with similar improvements across other configurations.

关键词： Degradation Runtime Clustering algorithms Routing partitioning algorithms Delays Field programmable gate arrays Video recording Convergence Clocks

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TBPart: An Effective Topological Order Balanced Hypergraph partitioning Algorithm for VLSI Processor-based Hardware Emulation

TBPart: An Effective Topological Order Balanced Hypergraph P...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Jing Tang Shunyang Bi Haonan Wu Hailong You School of Microelectronic Xidian University Xi’ an China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

As the complexity of circuit designs continues growing, processor-based emulation is becoming more and more popular for design verification. In a large-scale design, there are significant dependencies among the basic logic cells, which is represented as cells' topological order if the design is mapped to a graph. During the circuit partitioning stage, assigning the same topological order cells to one processor would significantly increase the delay of scheduling, further degrading the over-all performance. However, some well-known partitioners, like hMETIS and PaToH, mainly focus on cut size minimization without considering such topological order balance constraints, which limits their practical usage in processor-based hardware emulation. In this paper, we propose a partitioning algorithm TBPart considering the topological order balance to address the issue of wasting computational resources in hardware emulation. TBPart improves the topological balance of the partitioning results by considering the gain brought by vertices movement in improving the topological balance while also taking into account the cut-size loss, ensuring the quality of the cut-size while improving the topological balance of the partitioning results. We evaluate TBPart using the ISPD98 benchmark tests, and experimental results demonstrate its effectiveness in improving the topological order balance. On average hand, 0.26 times cut-size loss can result in a 2-fold improvement in topological order balance.

关键词： Design automation Processor scheduling Emulation Very large scale integration Minimization Hardware partitioning algorithms

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Deep Reinforcement Learning for Task partitioning and Partial Offloading in UAV Networks

Deep Reinforcement Learning for Task Partitioning and Partia...

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IEEE Conference on Vehicular Technology (VTC)

作者： Srivikas Varasala Veera Manikantha Rayudu Tummala Suhas N Reddy Sampath Kumar Talada Abhishek Hazra Mohan Gurusamy Computer Science and Engineering Indian Institute of Information Technology Sri City India Electrical and Computer Engineering National University of Singapore Singapore

ISBN: (数字)9798331517786

ISBN: (纸本)9798331517793

In recent times, Unmanned Aerial Vehicles (UAVs) have played a significant role in various fields like agriculture, defense, environmental monitoring, and many more. By minimizing the latency, energy consumption and improving the quality of services (QoS) while offloading the tasks, UAVs have played an outstanding role in the Internet of Things (IoT). Despite having a huge advantage, as the UAVs have limited computation, they cannot handle all the tasks that require intensive computation. To tackle the above problem, we have adopted the Deep Reinforcement Learning (DRL) technique in the UAV network, which helps in handling computationally expensive tasks by sharing the workload among the UAVs. The DRL-based strategy helps in reducing latency and energy consumption while maximizing the resource utilization of UAVs. Experiments have shown the significance of the adopted DRL strategy in reducing energy consumption by at least 16% compared to traditional algorithms.

关键词： Energy consumption Vehicular and wireless technologies Quality of service Autonomous aerial vehicles Deep reinforcement learning Blockchains partitioning algorithms Internet of Things Security Resource management

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Electric Vehicle Battery Virtual partitioning Algorithm for Residential Vehicle-to-Home Service

Electric Vehicle Battery Virtual Partitioning Algorithm for ...

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International Conference on Smart Energy Systems and Technologies (SEST)

作者： Andrea Bonfiglio Manuela Minetti Renato Procopio University of Genoa DITEN Genova Italy

ISBN: (数字)9798350386493

ISBN: (纸本)9798350386509

The current trend of electrification and transition to a sustainable and resilient electricity energy scenario is introducing new challenges and necessary improvements on the generation, transmission, distribution and end-user side. These changes require introducing novel solutions to exploit at maximum the potentials of the ongoing electrification of several sectors, especially at customer level. This paper proposes a novel Virtual partitioning Algorithm (VPA) dedicated to vehicles-to-home (V2H) service provided by private Electric Vehicles (EVs). The VPA will allow improving the environmental and economic performance of prosumers that have residential photovoltaic plants without the need of installing dedicated flexibility devices, e.g. battery energy storage systems (ST), or integrating existing storage units to expand the overall capacity without additional costs. This will help moving in the direction of a more sustainable energy scenario for buildings and energy systems also in the frame of novel configuration such as renewable energy communities. The proposed solution has been tested in a realistic residential setup with real data and the results highlighted the benefits from both the system integration and economic side.

关键词： Renewable energy sources Vehicle-to-grid Schedules Simulation System integration Production Electrification Charging stations Power markets partitioning algorithms

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