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Low-cost FFT Processor for DVB-T2 Applications

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2010年第4期56卷 2072-2079页

作者： Lin, Shin-Yo Wey, Chin-Long Shieh, Ming-Der Natl Cent Univ Dept Elect Engn Jhongli Taiwan Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan

An efficient Fast Fourier Transform (FFT) processor is greatly needed for real-time operation in many OFDM applications, such as xDSL, DAB, DVB-T/H, and etc. This paper presents a low-cost Parallel Memory-based FFT (PMB-FFT) processor for DVB-T2 applications. The processor has been designed and implemented in 90nm 1P9M CMOS process. Experimental results show that the PMB-FFT processor meets the DVB-T2 standard with N=32,768 points, and takes only 2.51 mm(2) in the core area with a power consumption of 0.89 mW at 25MHz.

关键词： Fast Fourier Transform Memory-based FFT processor Orthogonal Frequency Division Multiplexing DVB-T2 Parallel structure pipeline structure

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High-security asynchronous circuit implementation of AES

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第2期153卷 71-77页

作者： Shang, D Burns, F Bystrov, A Koelmans, A Sokolov, D Yakovlev, A Newcastle Univ Sch EECE Newcastle Upon Tyne NE1 7RU Tyne & Wear England

The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is achieved by avoidance of glitches and by data-independent switching behaviour. The design utilises a pipeline structure with built-in controllers and novel, highly balanced security latches.

关键词： cryptography asynchronous circuits self-timed dual-rail technology advanced encryption standard pipeline processing Cryptography Data security Logic and switching circuits high-security asynchronous circuit Logic circuits pipeline structure built-in controllers highly balanced security latches

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Damage Detection and Localization in pipeline Using Sparse Estimation of Ultrasonic Guided Waves Signals

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IFAC-PapersOnLine 2018年第24期51卷 941-948页

作者： Mountassir, Mahjoub El Mourot, Gilles Yaacoubi, Slah Maquin, Didier Institut de soudure Plateforme RDI CND 4 Bvd Henri BecquerelYutz57970 France Centre de Recherche en Automatique de Nancy CNRS Université de Lorraine 2 Avenue de la Forêt de Haye TSA 60604 54 518 France

This paper focuses on the development of a method for damage detection and localization in pipeline structures. These structures are subject to variation of environmental and operational conditions (EOCs) which have an impact on the collected signals. Since damage detection is generally based on comparison between the reference signals and the current signals acquired from the structure, the effects of EOCs will give rise to false alarm. This issue is addressed by selecting from the database of reference signals those with similar or very close EOCs. Such an operation can be performed by calculating a sparse estimation of the current signal. The estimation error is used as an indication of the presence of damage. Actually, a damage signal will be characterized by a high estimation error compared to that of a healthy signal. The position of the detected damage is obtained by calculating the estimation error on a sliding window over the damaged signal. This method was tested on signals collected on a small scale pipeline placed in laboratory conditions. Results have shown that the created damage was successfully detected and localized. © 2018

关键词： Damage detection Errors Guided electromagnetic wave propagation pipelines Signal processing Structural health monitoring Ultrasonic applications Detection and localization environmental Laboratory conditions localization Operational conditions pipeline structure Sparse estimation Ultrasonic guided wave

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Design and implementation of FFT/IFFT in IEEE 802.16d OFDM system

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Journal of Harbin Institute of Technology(New Series) 2009年第6期16卷 776-780页

作者：亓中瑞张浩邱昕刘壹陈杰 Institute of Microelectronics Chinese Academy of Sciences

The IEEE 802. 16 standard specifies the air interface of wireless metropolitan area network （WMAN）, and aims to provide wireless broadband access for integrated voice and video services. This paper presents the efficient design and implementation of fast Frouier transform （FFT） and inverse fast Frouier transform （IFFT） for the application in IEEE 802. 16d orthogoual frequency division multiplexing （OFDM） system. In this design, a novel pipeline structure for the branch of butterfly unit （BU） is proposed, which can improve the processing symbol rate by adding the number of branch flexibly. The symmetrical ping-pang structure of random access memory （RAM） is performed to increase the system throughput. Simulation results reveal that only with 1 branch of BU, the proposed FFF/IFFT design can almost achieve the maximum bandwidth requirement of IEEE 802. 16d OFDM system. And this design has been verified by FPGA and successfully implemented in the prototype of WiMAX transceiver.

关键词： FFT/IFFT OFDM pipeline structure branch of butterfly un-it symmetrical ping-pang structure

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New efficient design of digital comparator

New efficient design of digital comparator

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2nd International Conference on ASIC

作者： Wang, GJ Sheng, SM Ji, LJ Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)7543909405

Digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs manchester chain to fulfill the compare operation. Compared with the static implementations, MCP's highest operating frequency (125MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%similar to 22% lower than static version's. The layout area of MCP is only 87.6% of the static's. And it is very convenient to make up parallel or pipeline structure that is important for high performance VLSI design. Bg a series of optimizations the MCP gained a good noise immunity, Though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.

关键词： CMOS logic circuits VLSI integrated circuit design logic design comparators (circuits) integrated circuit noise digital comparator design MCP high performance VLSI design parallel structure pipeline structure noise immunity dynamic structure CMOS dynamic logic 125 MHz

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A pipeline Time-to-Digital Converter with a Programmable Time Amplifier

A Pipeline Time-to-Digital Converter with a Programmable Tim...

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IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE)

作者： Wang, Zixuan Xu, Hao Ding, Hao Xia, Xiaojuan Ji, Xincun Hu, Shanwen Guo, Yufeng Wang, Rong He, Haihang Nanjing Univ Posts & Telecommun Coll Elect & Opt Engn Nanjing Peoples R China Nanjing Univ Posts & Telecommun Coll Microelect Nanjing Peoples R China Jiangsu Lixing Gen Steel Ball Co Ltd Nantong Peoples R China

ISBN: (纸本)9781538635278

This paper presents a pipeline time-to-digital converter (TDC) using a programmable time amplifier (TA). The TA adds time intervals that contain quantization errors in different stages of the first conversion step to achieve time amplification. Therefore, the TA has advantages of programmability, good linearity and wide input range. The TDC is designed in a 65nm CMOS technology. A time resolution up to 5ps at 230MHz is achieved. The total power consumption is 3mW under a 1V supply.

关键词： Time-to-digital converter (TDC) pipeline structure programmable time amplifier quantization error pipeline structure digital phase-locked loop

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A NEW SIMPLE DIRECT COMPUTATION OF CUBIC CONVOLUTION SPLINE INTERPOLATION

A NEW SIMPLE DIRECT COMPUTATION OF CUBIC CONVOLUTION SPLINE ...

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IEEE International Conference on Image Processing (ICIP)

作者： Hong, Shao-Hua Wang, Lin Truong, Trieu-Kien Xiamen Univ Informat & Commun Engn Xiamen 361005 Fujian Peoples R China I Shou Univ Informat Engn Kaohsiung 840 Taiwan

ISBN: (纸本)9781728163956

It has been demonstrated that the cubic convolution spline interpolation (CCSI) scheme is one of the best algorithms for image resampling or compression. In this paper, a new simple direct computation of CCSI is proposed, where the sampled data are directly calculated by the use of the original data. Moreover, the proposed algorithm provides a regular and simple structure based on linear correlation and thus is naturally suitable for VLSI implementation. Computer simulations on several standard images indicate that the proposed simple direct computation of CCSI scheme can achieve almost the same objective and subjective performance with lower complexity.

关键词： CCSI low complexity pipeline structure simple direct computation algorithm

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Optimization of Serial-Serial Multiplier and Implementation of a 4-bit Multiplier 22

Optimization of Serial-Serial Multiplier and Implementation ...

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22nd Iranian Conference on Electrical Engineering (ICEE)

作者： Sabbagh, Sadegh Baseri, Javad Ferdowsi Univ Mashhad Integrated Circuit Lab Mashhad Iran Khavaran Univ Dept Elect Engn Mashhad Iran

ISBN: (纸本)9781479944095

In this article partial products algorithm of serial multipliers is presented and different architectures of these kinds of multipliers such as: Successive Addition, Serial-Parallel and Serial-Serial methods are surveyed. With respect to extension capability of pipeline architecture, this circuit is implemented as 4-bit serial-serial multiplier. Some problems have been found and issues were scrutinized. Through improvement in the architecture that is presented as a first method, the problems are eliminated. In following suggested way, it is optimized for speed and area usage of chip. Implementation, simulation and layout have been done by Cadence 6.1.0.243 with TSMC 0.18 mu m standard cell library. It is found by this improvement that with the total area usage of chip A=0.286nm(2) (result from W*L) and total power consumption P=3.6mW of power supply, maximum operation frequency is f(max)=700 MHz.

关键词： Serial-Serial Multiplier pipeline structure Partial Products TSMC 0.18 mu m

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AN FPGA HARDWARE IMPLEMENTATION FOR OMEGA-K SAR IMAGING ALGORITHM

AN FPGA HARDWARE IMPLEMENTATION FOR OMEGA-K SAR IMAGING ALGO...

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IEEE International Geoscience and Remote Sensing Symposium (IGARSS)

作者： Ding, Ning Zong, Zhulin Liu, Bolun Yuan, Shiwei Univ Elect Sci & Technol China Res Inst Elect Sci & Technol Chengdu Sichuan Peoples R China

ISBN: (纸本)9781665403696

This paper introduces the hardware design and implementation of Omega-K imaging algorithm. Based on the analysis of Omega-K algorithm theoretical derivation, we plan to use pipeline structure and soft IP multiplexed method to speed up the imaging speed and achieve the purpose of real-time imaging. By evaluating the hardware resources and system running time needed in the design, we can realize the real-time imaging. So, we select the appropriate hardware platform to implement. Finally, we verify the design scheme by using the actual radar echo data of 13 seconds. The experimental results show that the peak signal-to-noise ratio of the imaging results by the hardware platform is 39.23dB, and the imaging time of the hardware platform is 9.38 seconds. This shows that the imaging quality meets the requirements and the purpose of real-time imaging is achieved.

关键词： synthetic aperture radar (SAR) Omega-K pipeline structure soft IP multiplexed real-time imaging

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A Branch Predictor Design to Improve Prediction Rate by Reducing Index Aliasing in Application Processors 12

A Branch Predictor Design to Improve Prediction Rate by Redu...

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12th International Conference on Information and Communication Technology and System (ICTS)

作者： Park, Je Won Eun, Chang Min Cho, Hyun Hak Jeong, Ok Hyun Sogang Univ Dept Elect Engn Seoul South Korea

ISBN: (纸本)9781728121338

The current processors of mobile device are designed in a reduced instruction set computer (RISC) architecture. The branch instruction, which occupies 20 to 30% of RISC pipeline structure, is one of the main reasons of processor performance degradation. Failure to predict a branch causes a pipeline flush called a stall, and the processor will not be able to process the command during that cycle. Various branch predictors have been proposed;the conventional schemes such as global and local predictor have the disadvantages of wasting memory or having low prediction rates. Global predictors have low prediction rate due to index aliasing. Index aliasing is a phenomenon that makes wrong predictions due to overlapping indexes accessing the predictor. The proposed scheme is intended to reduce the occurrence of index aliasing by performing more XOR and addition operations in the index generation process than in conventional schemes. As a result, the proposed method has 0.69%p better prediction rate than the conventional method, which improves the processor performance. In this paper, the simulation was executed using the SimpleScalar 3.0 simulator and the benchmark program SPEC CPU2000. The experimental results show that when the cache size is 128KB currently used for smart phones, the proposed scheme has the best prediction.

关键词： Branch predictor Application processor Memory Size Prediction rate pipeline structure

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