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14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Wang, Chua-Chin Shih, Hsiang-Yu Wang, Wei Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 80424 Taiwan Chongqing Univ Posts & Telecommun CQUPT Coll Elect Engn Chongqing 400065 Peoples R China

ISBN: (纸本)9781538644416

A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The parabolic equations with proper selection of coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68,4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon,

关键词： ROM-less DDFS spurious free dynamic range (SFDR) parabolic polynomial interpolation pipeline structure frequency synthesizer

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Specific Hardware Implementation for Cofactorization in GNFS

Specific Hardware Implementation for Cofactorization in GNFS

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International Conference on Computer, Information and Telecommunication Systems (CITS)

作者： Yu, Haibo Bai, Guoqiang Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781509006908

Cofactorization, checking smoothness of mid-size integers, is usually adopted in General Number Field Sieve. In this paper, we present a specific cofactorization hardware implementation, which performs smoothness test for mid-size integers at a much higher throughput than previous works. The proposed design, based on highly-parallel and pipeline structure, can analysis a 125-bit integer and determine in less than 130 clock cycles whether it could factor completely over a factor base. Besides, the algorithm used in architecture can be performed by multiplication, addition and some logical operations only, which brings simple circuit structure, low hardware cost and short time delay. Moreover, the comparison results show that our architecture achieves a speedup of one or two orders of magnitude over implementation based on Elliptic Curve Method. Our design therefore can be a good solution to cofactorization.

关键词： Cofactorization smoothness test prime factor divisibility pipeline structure

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Efficient Integrated Circuit Design for High Throughput AES 13th

Efficient Integrated Circuit Design for High Throughput AES

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13th International Scientific Conference on Future Information Technology (FutureTech)

作者： Antwi, Alexander O. A. Ryoo, Kwangki Hanbat Natl Univ Grad Sch Informat & Commun 125 Dongseodaero Daejeon 34158 South Korea

ISBN: (纸本)9789811313288;9789811313271

Advanced Encryption Standard (AES) has been adopted widely in most security protocols due to its robustness till date. It would thus serve well in IoT technology for controlling the threats posed by unethical hackers. This paper presents a hardware-based implementation of the AES algorithm. We present a four-stage pipelined architecture of the encryption and key generation. This method allowed a total plaintext size of 512 bits to be encrypted in 46 cycles. The proposed hardware design achieved a maximum frequency of 1.18 GHz yielding a throughput of 13 Gbps and 800 MHz yielding a throughput of 8.9 Gbps on the 65 and 180 nm processes respectively.

关键词： pipeline structure Symmetric key cryptography Advanced encryption standard

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Full Hardware Image Encryption for Oscillating Memristor Circuits

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ADVANCED MATERIALS TECHNOLOGIES 2023年第6期8卷

作者： Wang, Lu Qu, Jiaxin Li, Jiazhuang Wen, Dianzhong Heilongjiang Univ Sch Elect Engn Harbin 150080 Peoples R China

Al/PMMA/CS/PMMA/ITO structure devices are fabricated using polymethyl methacrylate (PMMA) and chitosan (CS) as dielectric layer materials. Its electrical characteristics and conductive mechanism are studied using its own physical characteristics to build a memristor true random number generator (TRNG). The generated true random sequence is optimized by a field programmable gate array (FPGA), and the optimized random number sequence is tested by the National Institute of Standards and Technology (NIST) to analyze its randomness. The pipeline structure is introduced to optimize the whole image encryption system, and the optimized random number sequence is used to realize image encryption inside the FPGA. Then, the encrypted image is displayed on a liquid crystal display (LCD) screen to realize random number generation and image encryption of all hardware. Finally, the encrypted image is analyzed.

关键词： image encryption memristor pipeline structure

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A 4500 MIPS/W, 86μA resume-standby, 11 μA ultra-standby application processor for 3G cellular phones

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IEICE TRANSACTIONS ON ELECTRONICS 2005年第4期E88C卷 528-535页

作者： Ishikawa, M Kamei, T Kondo, Y Yamaoka, M Shimazaki, Y Ozawa, M Tamaki, S Furuyama, M Hoshi, T Arakawa, F Nishii, O Hirose, K Yoshioka, S Hattori, T Hitachi Ltd Cent Res Lab Kokubunji Tokyo 1858601 Japan Rensas Technol Corp Kodaira Tokyo 1878588 Japan SuperH Japan Ltd Kodaira Tokyo 1870022 Japan

We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. for low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at LOV power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through mu I/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 mu A. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully rec

关键词： application processor cellular phone pipeline structure resume-standby low power low leakage

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A pipeline chip for Quasi Arithmetic coding

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第4期E84A卷 1034-1041页

作者： Wiseman, Y Bar Ilan Univ Dept Math & Comp Sci IL-52900 Ramat Gan Israel Jerusalem Coll Technol Dept Comp Engn IL-91160 Jerusalem Israel

A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of tile compression efficiency.

关键词： pipeline structure compression arithmetic coding hardware-software combination

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DEPOSITION RATE AND PURIFICATION EFFECT OF ATMOSPHERIC PARTICLE BY DIFFERENT pipeline CONNECTION FORMS

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THERMAL SCIENCE 2024年第2A期28卷 961-970页

作者： Xu, Yi Zhang, Xin Gao, Yun Yu, Tao Ren, Fei He, Puchun Li, Mengyue Xian Univ Architecture & Technol Sch Resources Engn Xian Peoples R China Wuhan Second Ship Design & Res Inst Wuhan Peoples R China XAUAT Engn Technol Co Ltd Xian Peoples R China Shaanxi Prov Land Engn Construct Grp Co Ltd Yanan Branch Yanan Peoples R China Xian Ziwei Real Estate Dev Co Ltd Xian Peoples R China

The connection form of pipelines has an important impact on the comprehensive performance evaluation of fresh air systems. The most used PVC fresh air pipeline material in the market was selected for experimental research in this paper, and the deposition rates of particles of different pipeline connection form of 45 degrees, 90 degrees bend, and straight tee were all tested and compared. The purification effect of the pipeline connection form of the highest deposition rate is tested and studied. The results showed that the particle deposition rates were the highest in the connection form of straight tee, with deposition rates of 47.61%, 18.06%, and 8.13% for PM10, PM2.5, and PM1.0, respectively. As the particle size increases, the deposition rate of particles also gradually increases. The larger the inlet velocity, the greater the deposition rate. The particle concentration on the outlet of the pipeline in the connection forms of straight tee was significantly decreased after adding the purification equipment, and the deposition rates of PM10, PM2.5, and PM1.0 decreased by 45.01%, 68.89%, and 77.48%. Therefore, the use of pipeline elbows should be reduced, and purification equipment should be installed in the process of using, which will reduce the deposition of particles in the fresh air systems.

关键词： pipeline structure PVC particles deposition rate purification effect

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The optimum pipeline depth of a microprocessor for low energy consumption

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 2005年第1期88卷 1-11页

作者： Magoshi, H Hyodo, A Murakami, K Kyushu Univ Dept Informat Grad Sch Informat Sci & Elect Engn Kasuga Fukuoka 8168580 Japan Kyushu Univ Dept Comp Sci & Commun Engn Grad Sch Informat Sci & Elect Engn Kasuga Fukuoka 8168580 Japan

The number of pipeline stages that minimize the energy consumption in pipeline processors is studied based on a mathematical performance model, and the conditions are examined. We examine the Energy Per Instruction (E-PI) when given the clock cycle time and the minimum power supply voltage required for operation where the execution times per instruction will be equal for processor models having different numbers of stages. In processors targeting low energy consumption, the optimum number of pipeline stages is five or less when the rate of increase in the circuit load capacitance is 10% as the number of stages increases. pipeline hazards such as branch prediction misses have a substantial effect on the energy consumption and the optimum minimum number of stages. The latch overhead time, which depends on the circuit design technology, has little effect. (C) 2004 Wiley Periodicals, Inc.

关键词： pipeline structure pipeline depth optimized design low energy consumption design microprocessor

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A Real-Time Imaging Algorithm Based on Sub-Aperture CS-Dechirp for GF3-SAR Data

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SENSORS 2018年第8期18卷 2562页

作者： Sun, Guang-Cai Liu, Yanbin Xing, Mengdao Wang, Shiyu Guo, Liang Yang, Jun Xidian Univ Natl Lab Radar Signal Proc Xian 710071 Shaanxi Peoples R China Xidian Univ Sch Phys & Optoelect Engn Xian 710071 Shaanxi Peoples R China Xian Univ Sci & Technol Coll Geomat Xian 710054 Shaanxi Peoples R China

Conventional synthetic aperture radar (SAR) imaging algorithms usually require a period of time to process data that is longer than the time it takes to record one synthetic aperture or that corresponding to an adequate azimuth resolution. That is to say, the real-time processing system is idle during the long data recording time and the utilization of computational resources is low. To deal with this problem, a real-time imaging algorithm based on sub-aperture chirp scaling dechirp (CS-dechirp) is proposed in this paper. With CS-dechirp, the sub-aperture data could be processed to form an image with relatively low resolution. Subsequently, a few low-resolution images are generated as longer azimuth data are recorded. At the stage of full-resolution image generation, a coherent combination method for the low-resolution complex-value images is developed. As the low-resolution complex-value images are coherently combined one by one, the resolution is gradually improved and the full-resolution image is finally obtained. The results of a simulation and real data from the GF3-SAR validate the effectiveness of the proposed algorithm.

关键词： GF3-SAR real-time CS-dechirp coherently combination pipeline structure

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Structural Outlooks for the OTIS-Arrangement Network

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INTERNATIONAL JOURNAL OF GRID AND HIGH PERFORMANCE COMPUTING 2011年第2期3卷 59-68页

作者： Awwad, Ahmad Al-Sadi, Jehad Haddad, Bassam Kayed, Ahmad Fahad Bin Sultan Univ Tabuk Saudi Arabia Arab Open Univ Amman Jordan Univ Petra Amman Jordan

Recent studies have revealed that the Optical Transpose Interconnection Systems (OTIS) are promising candidates for future high-performance parallel computers. This paper presents and evaluates a general method for algorithm development on the OTIS-Arrangement network (OTIS-AN) as an example of OTIS network. The proposed method can be used and customized for any other OTIS network. Furthermore, it allows efficient mapping of a wide class of algorithms into the OTIS-AN. This method is based on grids and pipelines as popular structures that support a vast body of parallel applications including linear algebra, divide-and-conquer types of algorithms, sorting, and FFT computation. This study confirms the viability of the OTIS-AN as an attractive alternative for large-scale parallel architectures.

关键词： Arrangement-Star Network Grid structure Interconnection Networks OTIS pipeline structure

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