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A pipeline architecture FOR FACTORING LARGE INTEGERS WITH THE QUADRATIC SIEVE ALGORITHM

SIAM JOURNAL ON COMPUTING 1988年第2期17卷 387-403页

作者： POMERANCE, C SMITH, JW TULER, R UNIV GEORGIA DEPT COMP SCIATHENSGA 30602

We describe the quadratic sieve factoring algorithm and a pipeline architecture on which it could be efficiently implemented. Such a device would be of moderate cost to build and would be able to factor 100-digit numbers in less than a month. This represents an order of magnitude speed-up over current implementations on supercomputers. Using a distributed network of many such devices, it is predicted much larger numbers could be practically factored.

关键词： 11Y05 68M05 pipeline architecture factoring algorithms quadratic sieve

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pipeline architecture for Mobile Data Analysis

Pipeline Architecture for Mobile Data Analysis

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International Conference on Information Networking (ICOIN)

作者： Conceicao, Arlindo F. Sanchez, Jimmy V. dos Santos, Bruno G. Vieira, Dario Rocha, Vladimir Fed Univ Sao Paulo UNIFESP Inst Sci & Technol Sao Jose Dos Campos Brazil Ecole Ingn Informat & Technol Numer Efrei F-94800 Paris France Univ Sao Paulo Sao Paulo SP Brazil

ISBN: (纸本)9781479936892

This paper presents a cloud architecture that allows collecting and analyzing mobile data. The system offers simple and intuitive interfaces to create mobile applications (Apps), without the need for any programming skill to develop them. The platform allows the collection of conventional data, such as numbers and text, and also non-conventional data, such as multimedia files, location information, and barcodes. The collected data can be shared among users on a social network. In addition, we propose a pipeline architecture to data analyzing.

关键词： cloud computing data analysis mobile computing social networking (online) barcodes cloud architecture conventional data location information mobile applications mobile data analysis multimedia files nonconventional data numbers pipeline architecture social network text Androids Computer architecture Data collection Mobile communication Mobile handsets Servers XML

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GAMORRA: An API-level workload model for rasterization-based graphics pipeline architecture

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COMPUTERS & GRAPHICS-UK 2022年 106卷 9-19页

作者： Mohammadi, Iman Soltani Ghanbari, Mohammad Hashemi, Mahmoud Reza Univ Tehran Sch Elect & Comp Engn Tehran 14395515 Iran Univ Essex Sch Comp Sci & Elect Engn Colchester CO4 3SQ Essex England

The performance of applications that require frame rendering time estimation or dynamic frequency scaling, rely on the accuracy of the workload model that is utilized within these applications. Existing models lack sufficient accuracy in their core model. Hence, they require changes to the target application or the hardware to produce accurate results. This paper introduces a mathematical workload model for a rasterization-based graphics Application Programming Interface (API) pipeline, named GAMORRA, which works based on the load of each stage of the pipeline. Firstly, GAMORRA models the load of each stage of the pipeline based on their input data size. Then, the calculated workloads of the stages are fed to a Multiple Linear Regression (MLR) model as explanatory variables. A hybrid offline/online training scheme is proposed as well to train the model. A suite of benchmarks is also designed to tune the model parameters based on the performance of the target system. The experiments were performed on Direct3D 11 and on two different rendering platforms comparing GAMORRA to an AutoRegressive (AR) model, a Frame Complexity Model (FCM) and a frequency-based (FRQ) model. The experiments show an average of 1.27 ms frame rendering time estimation error (9.4%) compared to an average of 1.87 ms error (13.2%) for FCM which is the best method among the three chosen methods. However, this comes at the cost of 0.54 ms (4.6%) increase in time complexity compared to FCM. Furthermore, GAMMORA improves frametime underestimations by 1.1% compared to FCM. (c) 2022 Published by Elsevier Ltd.

关键词： Workload modeling Rendering time estimation Graphics API pipeline architecture

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A pipeline architecture for computing the Euler number of a binary image

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JOURNAL OF SYSTEMS architecture 2005年第8期51卷 470-487页

作者： Bishnu, A Bhattacharya, BB Kundu, MK Murthy, CA Acharya, T Indian Stat Inst Ctr Soft Comp Res Kolkata 700108 India Japan Adv Inst Sci & Technol Tatsunokuchi Ishikawa 9231292 Japan Avisere Inc Tucson AZ 85711 USA

Euler number of a binary image is a fundamental topological feature that remains invariant under translation, rotation, scaling, and rubber-sheet transformation of the image. In this work, a run-based method for computing Enter number is formulated and a new hardware implementation is described. Analysis of time complexity and performance measure is provided to demonstrate the efficiency of the method. The sequential version of the proposed algorithm requires significantly fewer number of pixel accesses compared to the existing methods and tools based on bit-quad counting or quad-tree, both for the worst case and the average case. A pipelined architecture is designed with a single adder tree to implement the algorithm on-chip by exploiting its inherent parallelism, The architecture uses O(N) 2-input gates and requires O(NlogN) time to compute the Euler number of an N x N image. The same hardware, with minor modification, can be used to handle arbitrarily large pixel matrices. A standard cell based VLSI implementation of the architecture is also reported. As Euler number is a widely used parameter, the proposed design can be readily used to save computation time in many image processing applications. (c) 2005 Elsevier B.V. All rights reserved.

关键词： Euler number image processing pipeline architecture VLSI implementation

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A Load-Balanced pipeline architecture for IP Route Lookup

A Load-Balanced Pipeline Architecture for IP Route Lookup

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IEEE Computing, Communications and IT Applications Conference (IEEE ComComAp)

作者： Hu, Shengqing Wu, Yi Nong, Ge Sun Yat Sen Univ Dept Comp Sci Guangzhou 510275 Guangdong Peoples R China

ISBN: (纸本)9781467360449;9781467360432

We present in this article a pipeline architecture built with multiple memory blocks for IP route lookup using trie-based routing algorithms. A two-hierarchy prefix distribution scheme is employed to balance the storage demands among the memory blocks, where prefixes not longer than r bits in the routing table are mapped to an index table and the remaining prefixes are organized into multiple prefix tries according to their highest r bits. An access control strategy is employed to avoid access conflicts in the routing system when multiple packets attempt to access a same memory block. For this purpose, a load balancer consisting of two groups of buffers connected by a rotator, is employed to distribute to memory blocks the searching requests of IP lookups for arriving packets. The simulation results indicate that the proposed multi-block pipeline routing architecture can achieve nearly 100% throughput under typical IPv4 corpora with uniform distributed destinations.

关键词： Route lookup pipeline architecture prefix trie load balance 100% throughput

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High speed Reed-Solomon decoder with pipeline architecture

High speed Reed-Solomon decoder with pipeline architecture

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International Conference on Wireless and Optical Communications Networks

作者： Kavian, YS Falahati, A Khayatzadeh, A Naderi, M IUST Tehran Iran

ISBN: (纸本)0780390199

Quality of service (QoS) is one of the most important factors in mobile communication networks. Decreasing of delay, including processing time, and error correction are proposed to get higher QoS in mobile networks. Reed-Solomon coding is one of the most important schemes for this purpose, for error correction. In this paper a pipeline approach of RS decoder is proposed to reduce the processing time. In the pipeline architecture of Reed-Solomon decoder two schemes are proposed, first the Reed-Solomon decoder is developed in five stages pipeline, then to reduce the data dependencies between stages, it is developed by three stages pipeline. Because of the data dependency between the stages, it is impossible to achieve ideal speedup. In the five-stage pipeline scheme of RS decoder the data dependency has been caused the %18.5 loss in the speedup, this value for the three-stage pipeline scheme is about %14. The hardware description language (HDL) method is employed to hardware synthesis the Reed-Solomon decoder on FPGA chips.

关键词： coding Reed-Solomon coding pipeline architecture HDL FPGA

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A Scalable pipeline architecture for IPv4/IPv6 Route Lookup

A Scalable Pipeline Architecture for IPv4/IPv6 Route Lookup

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18th IEEE International Conference on Networks (ICON)

作者： Wu, Yi Nong, Ge Sun Yat Sen Univ Dept Comp Sci Guangzhou 510275 Guangdong Peoples R China

ISBN: (纸本)9781467345231;9781467345217

When the Internet is evolving from IPv4 to IPv6, there is a need in practice for route lookup algorithms that can simultaneously support IPv4 and IPv6 packets. A scalable pipeline routing architecture for route lookups of IPv4/IPv6 packets using a prefix trie is studied in this work. In this routing architecture, a routing table is mapped into an index table and a number of prefix tries. Each prefix trie is further divided into multiple subtries, where two copies are maintained for each subtrie. Specifically, each subtrie has two copies rooted in two different memory blocks. For each copy of a subtrie, the root node is stored in a randomly selected memory block and the other descendant nodes are cyclically stored in the subsequent memory blocks in a manner of one level per block. The scheduling problem in such an architecture is modeled as bipartite matching between packets and memory blocks. For performance evaluation, extensive simulation experiments have been conducted for typical IPv4 and IPv6 corpora. The simulation results indicate that this routing architecture can achieve high system's throughputs under both IPv4 and IPv6 traffic loads.

关键词： IPv4/IPv6 route lookup pipeline architecture prefix trie bipartite matching

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MPC-PAT: A pipeline architecture for Beaver Triple Generation in Secure Multi-party Computation 8

MPC-PAT: A Pipeline Architecture for Beaver Triple Generatio...

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8th IEEE International Test Conference in Asia (ITC-Asia)

作者： Li, Xiaolin Yan, Wei Liu, Hongwei Zhang, Yong Hao, Qinfen Liu, Yong Sun, Ninghui Chinese Acad Sci Inst Comp Technol Beijing Peoples R China Chinese Acad Sci Beijing Peoples R China Zhongguancun Lab Beijing Peoples R China

ISBN: (纸本)9798331540340;9798331540333

Secure Multi-Party Computation (MPC) is proposed to protect the data privacy from a group of parties, enabling collaborative computation of correct results for target functions. SPDZ, a set of mature MPC protocols widely used in machine learning and other scenarios, requires a significant number of Beaver triples for secure multiplications among parties. Given no Trusted Third Party (TTP) participated, the generation time constitutes over 92% of the total running time. This paper introduces MPC-PAT, a high-performance pipeline architecture designed for efficient Beaver triple generation. MPC-PAT accelerates random number generation, hash function, and modular multiplication(MM) in two finite fields. The evaluation results from its FPGA implementation demonstrate 99x speed-up for basic operations and 136x speed-up for various convolutional networks compared to the existing SPDZ works.

关键词： MPC SPDZ Beaver triple pipeline architecture

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Fast Writing Strategy of STT-MRAM With pipeline architecture

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IEEE TRANSACTIONS ON MAGNETICS 2022年第8期58卷

作者： Zhang, Guangjun Jiang, Yanfeng Jiangnan Univ Dept Elect Engn Wuxi 214122 Jiangsu Peoples R China Jiangnan Univ Internet Things Engn Coll Dept Microelect Wuxi 214122 Jiangsu Peoples R China

A fast writing strategy of spin transfer torque (STT) magnetic random access memory (STT-MRAM) combined with pipeline architecture and early write termination (EWT) technology is proposed in this article. Both the writing speed and the writing power consumption of STT-MRAM are optimized. First, based on the proposed pipeline structure, the writing operation can be conducted within a single clock cycle, much decreasing the writing time. Second, the EWT technology is adopted in the writing operation. In the traditional operation of STT-MRAM, the same data are repeatedly written to the memory cell, which wastes the writing power consumption and the writing operation time. In this article, combined with the EWT technology and the pipeline architecture, the unnecessary writing power is reduced by 92.8%, while the necessary writing power is increased by 19.8%. Taking 32 kb data for the writing operation, the operation speed of the new writing strategy is increased by 67.4% compared with the incumbent writing technology. The proposed strategy has potential application in the embedded STT-MRAM acting as cache memory in the computer system.

关键词： Early write termination (EWT) pipeline architecture spin transfer torque (STT) magnetic random access memory (STT-MRAM) write circuit

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EPA: The effective pipeline architecture for CNN accelerator with high performance and computing efficiency based on FPGA

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2023年第18期35卷

作者： Zhang, Junjie Yin, Qiao Hu, Weicheng Li, Yunfeng Li, Hu Ye, Nan Cao, Bingyao Shanghai Univ Key Lab Specialty Fiber Opt & Opt Access Network Joint Int Res Lab Specialty Fiber Opt & Adv Commu Shanghai 200072 Peoples R China

Thanks to the great developments of the latest Field Programmable Gate Array (FPGA), the performance bottleneck of Deep Learning hardware accelerators has been converted to computing ability. In this paper, a novel FPGA-based Convolutional Neural Network (CNN) Accelerator architecture, named the Effective pipeline architecture (EPA) is proposed to optimize the resource usage for the implementation of the CNN calculation. As the unique storage strategies, which contain many creative designing details, are adopted and optimized for different CNN models and layers, great DSP computing efficiency can be achieved in the fine-grained pipeline. Moreover, compared with the traditional architectures, through the kernel combination and data scheduling, twice throughput for the general matrix multiplication is realized in a great many parallel DSP48E resources. As a result, the realization of Yolov2-Tiny achieves 873 Giga Operations Per Second (GOPS) by 902 DSPs with 67 Frames Per Second (FPS), and the computing efficiency in most layers can even reach more than 90%, which improves the calculation performance and efficiency comparing with the previous designs, and is significant to meet the increasing computing requirement.

关键词： CNN accelerator computing efficiency fine‐ grained pipeline FPGA high performance pipeline architecture

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