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7th International Conference on Wavelet Analysis and Pattern Recognition

作者： Chou, Fu-Hua Huang, Jie-Cyun Ching Yun Univ Dept Elect Engn Tao Yuan 320 Taiwan

ISBN: (纸本)9781424437276

In this paper, a pipelining empirical mode decomposition is presented to reduce the computing time of the emotionalized spontaneous speaker or speech recognition processing. This is a novel approach for integrating the pipelining technique into the standard empirical mode decomposition of the Hilbert-Huang transform. In addition, there is reduced about 45% of the computing time when the emotionalized spoken signal through our segmentation and pipelining processes. Based on the designed processing of emotionalized spontaneous speaker or speech recognition, the segmented and processed voice signals arc recomposed back for constructing the speech and speaker models, or to identify which existed model is the most similar one. In the final part of this paper, a comparison of the speech recognized rate between standard and pipelining empirical mode decompositions are presented, and an equivalent effect in the recognition will be found. In practice, speaker or speech recognitions in an emotionalized spontaneous speech are very difficult. The existing speech recognition methods often fail to capture inherent voiceprint features from an emotionalized speech, such as the voice with a passionate intonation. And some of the existed methods to extract the pure voiceprint from an emotionalized spoken signal are very expensive in computation and time, so that technique is impossible to use in a real-time environment like smart houses. But, this paper presents a solution to improve the emotionalized spontaneous speaker or speech recognition processing to fit the real-time request.

关键词： pipelining processing Empirical Mode Decomposition Emotionalized Spoken Signal processing Speech Recognition Intrinsic Mode Function

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Design of infrared data acquisition and processing system

Design of infrared data acquisition and processing system

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IEEE 1996 National Aerospace and Electronics Conference (NAECON 1996)

作者： Zhang, L He, SH Zhuang, ZW NATL DEF UNIV ATR LABINST ELECTR ENGNCHANGSHA 410073HUNANPEOPLES R CHINA

ISBN: (纸本)0780333071

A data acquisition and processing system for sixteen infrared light-detection signals is introduced, which can processes sixteen infrared target signals real time, and achieves identification and tracing of target signals. The system uses four TMS320C25 as host processor, achieves synchronous parallel processing and possesses powerful anti-interference performance. The system uses three-level pipeline operation and adapts real-time processing.

关键词： data acquisition data processing real-time system parallel processing pipelining processing

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Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

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IEEE TRANSACTIONS ON SIGNAL processing 2000年第9期48卷 2712-2716页

作者： Ma, J Parhi, KK Hekstra, GJ Deprettere, EF Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA Philips Res Labs Eindhoven Netherlands Leiden Univ Leiden Inst Adv Comp Sci Leiden Netherlands

In this correspondence, an efficient implementation of pipelined coordinate rotation digital computer (CORDIC)-based IIR digital filters based on fast orthonormal mu-rotations is proposed. Using this method, the Givens rotations are approximated by angles corresponding to orthonormal mu rotations, which are based on the idea of CORDIC and can perform rotation with minimal number of shift-add operations. We present various methods of construction for such orthonormal mu rotations. A significant reduction (over 70%) of the number of required shift-add operations is achieved. All types of fast rotations can be implemented as a cascade of only four basic types of shift-add stages. These stages can be executed on a modified Boating-point CORDIC architecture, making the pipelined filter highly suitable for VLSI implementations.

关键词： IIR digital filters Jacobian matrices orthogonal transforms pipelining processing

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High Level Model of Time Predictable Multitask Control Unit 13

High Level Model of Time Predictable Multitask Control Unit

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13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems

作者： Golly, Lukasz Milik, Adam Pulka, Andrzej Silesian Tech Univ Inst Elect Dept Automat Control Elect & Comp Sci Ul Akad 16 Gliwice Poland

The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system. The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem arc given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units arc illustrated on examples. The main memory access control unit and the original memory system organization arc described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Real-time systems Embedded systems Multiprocessing systems pipelining processing Parallelism Concurrency Multithreading and multitasking Time predictable machines

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Dynamic Rescheduling of Tasks in Time Predictable Embedded Systems

Dynamic Rescheduling of Tasks in Time Predictable Embedded S...

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11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems (PDeS)

作者： Pulka, Andrzej Milik, Adam Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland

ISBN: (纸本)9783902823144

The work concerns an approach to the multi-threading and multitasking problem. The main research objective of the time predictable real-time systems is identified. A brief summary of the related works is given. Idea of thread interleaving is described and the architecture of the proposed time predictable embedded system is presented. The solution of the dynamic interleave controller of threads (DICT) with dynamically modified (reconfigured) priorities of tasks (threads) is analyzed. The paper investigates the model of the system and gives its simulation results. The entire system is synthesized in the hardware structure. Some experiments with that emphasize advantages of the proposed hardware implementation

关键词： Real-time systems Embedded systems Multiprocessing systems pipelining processing Parallelism Concurrency Multithreading and multitasking Time predictable machines

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Dynamic Rescheduling of Tasks in Time Predictable Embedded Systems

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IFAC Proceedings Volumes 2012年第7期45卷 305-310页

作者： Andrzej Pułka Adam Milik Institute of Electronics Silesian University of Technology ul. Akademicka 16 44-100 Gliwice Poland. (Tel: +48 32-237-1644 +48-32-237-1495)

关键词： Real-time systems Embedded systems Multiprocessing systems pipelining processing Parallelism Concurrency Multithreading and multitasking Time predictable machines

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High Level Model of Time Predictable Multitask Control Unit

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IFAC-PapersOnLine 2015年第4期48卷 348-353页

作者： Łukasz Golly Adam Milik Andrzej Pulka Institute of Electronics Department of Automatic Control Electronics and Computer Science Silesian University of Technology Gliwice ul.Akademicka 16 Poland

The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system, The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem are given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units are illustrated on examples. The main memory access control unit and the original memory system organization are described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model.

关键词： Real-time systems Embedded systems Multiprocessing systems pipelining processing Parallelism Concurrency Multithreading and multitasking Time predictable machines

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Design and Implementation of Optimizing SRAM Area in TFT Driver IC

Design and Implementation of Optimizing SRAM Area in TFT Dri...

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2012 International Conference on Environmental Engineering and Technology(ICEET2012)

作者： Hui-gang Wang,Qing-ming Yi,Yu-jing Li College of Information Science and Technology Actions-Jinan University Integrated Circuit Design Joint Laboratory Guangzhou,China

A circuit design program for TFT driver IC with the image compression based on DCT is proposed in this *** storage is reduced by adding DCT compression circuit in which the data is compressed before sending to SRAM and decompressed when sending out from *** power design in gating clock is implemented for reducing power *** scheme based on the independent R,G,B color is used for reducing data operation *** result shows that area of SRAM in chip is reduced when the picture data with the same quality is displayed.

关键词： DCT compression TFT-LCD pipelining processing VERA verification

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