检索结果-内蒙古大学图书馆

An Area-Efficient Hybrid polar decoder With Pipelined Architecture

IEEE ACCESS 2020年 8卷 68068-68082页

作者： Wang, Yu Wang, Qinglin Zhang, Yang Qiu, Shikai Xing, Zuocheng Natl Univ Def Technol Natl Lab Parallel & Distributed Proc Changsha 410073 Peoples R China

As the first kind of capacity-achieving forward error correction (FEC) codes, polar codes have attracted much research interest recently. Compared with traditional FEC codes, polar codes show better error correction performance when successive cancellation list (SCL) decoding with cyclic redundancy check is adopted. However, its serial decoding nature and high complexity of list management lead to its low throughput. Though the adaptive SCL decoding and hybrid decoding can improve the throughput, it comes at cost of implementation area. In this paper, we propose a pipelined hybrid decoding procedure and the corresponding hardware architecture to improve the area efficiency. In our design, the idle decoding cores are employed for successive cancellation (SC) decoding when SCL decoding is not working. The SCL decoding will be activated when the SC decoding fails. Different decoding cores work according to their own operation sequences and share one common processing array to improve the utilization ratio of processing elements. Constant receiving interval is supported with the design of input buffer to store all received codewords. A software platform is established to optimize the design parameters for each module of decoder. Moreover, the corresponding architecture is implemented using 65nm technology. Experimental results show that the proposed decoder can achieve a similar error correction performance with the SCL decoding with list size 16. Compared to the state-of-the-art available hybrid decoder, our proposed pipelined hybrid decoder is 3.07 x more area efficient.

关键词： polar decoder hybrid decoding pipelined architecture area-efficient

来源：评论

学校读者我要写书评

暂无评论

Syndrome-Enabled Unsupervised Learning for Neural Network-Based polar decoder and Jointly Optimized Blind Equalizer

引用

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2020年第2期10卷 177-188页

作者： Teng, Chieh-Fang Chen, Yen-Liang Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan MediaTek Inc Hsinchu 30078 Taiwan

Recently, the syndrome loss has been proposed to achieve "unsupervised learning" for neural network-based BCH/LDPC decoders. However, the design approach cannot be applied to polar codes directly and has not been evaluated under varying channels. In this work, we propose two modified syndrome losses to facilitate unsupervised learning in the receiver. Then, we first apply it to a neural network-based belief propagation (BP) polar decoder. With the aid of CRC-enabled syndrome loss, the BP decoder can even outperform conventional supervised learning methods in terms of block error rate. Secondly, we propose a jointly optimized syndrome-enabled blind equalizer, which can avoid the transmission of training sequences and achieve global optimum with 1.3 dB gain over non-blind minimum mean square error (MMSE) equalizer.

关键词： Neural network polar decoder unsupervised learning syndrome loss blind equalizer joint optimization

来源：评论

学校读者我要写书评

暂无评论

Towards More Secure PUF Applications: A Low-Area polar decoder Implementation 35

Towards More Secure PUF Applications: A Low-Area Polar Decod...

引用

35th IEEE International System-on-Chip Conference (SOCC)

作者： Kestel, Claus Frisch, Christoph Pehl, Michael Wehn, Norbert Univ Kaiserslautern Dept Elect & Comp Engn D-67663 Kaiserslautern Germany Tech Univ Munich Dept Elect & Comp Engn D-80333 Munich Germany

ISBN: (数字)9781665459853

ISBN: (纸本)9781665459853

Physical unclonable functions (PUFs) are security primitives that rely on random manufacturing variations. In comparison to secure non-volatile memory, PUFs offer the same functionality for storing a cryptographic key but with a lower cost. This makes them especially interesting for systems with limited resources. Deriving a reliable key from a noisy PUF requires an error correction code. In recent years, several works have suggested polar codes for PUFs pointing to security benefits of this code class. However, none of them provided a hardware implementation, which additionally has to match the low-cost nature of PUFs, i.e., very small area. Since polar decoders are more complex compared to other codes like algebraic codes used for PUFs, the practical applicability of polar codes remained uncertain. This work shows for the first time that polar code implementations are well suited for PUFs. Our polar decoder implementation, which is optimized for PUFs, shows a total area of only 4.2k mu m(2) in a 22nm technology.

关键词： polar Code polar decoder Physical Unclonable Function Implementation Hardware ASIC

来源：评论

学校读者我要写书评

暂无评论

Code Length Compatible Belief Propagation polar decoder Based on Folding and Unfolding

Code Length Compatible Belief Propagation Polar Decoder Base...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Li, Muhao Wang, Huizheng Shen, Yifei Tan, Xiaosi Zhang, Chuan Southeast Univ Lab Efficient Architectures Digital Commun & Sign Natl Mobile Commun Res Lab Nanjing Peoples R China Purple Mt Labs Nanjing Peoples R China

ISBN: (纸本)9798350330991;9798350331004

This paper presents a code-length compatible architecture for belief propagation (BP) polar decoders. This decoder incorporates folding and unfolding techniques with control signals, allowing it to decode codes with varying code lengths. By modifying the architecture originally designed for code length N, the proposed decoder can handle codes of length 2(i)N, where i is an element of Z(+) using folding, and i is an element of Z(-) using unfolding. To reduce the critical path and implementation complexity, a new routing design is proposed. Moreover, we introduce a memory architecture utilizing shift registers instead of RAM to increase the throughput. We demonstrate gate-level implementations to illustrate the design's architecture. Finally, we analyze the throughput, area, and power consumption of the decoders. Compared with traditional single-column designs with N = 1024, the proposed decoder architecture can achieve up to 136% hardware efficiency while consuming 1.6% less area.

关键词： Belief propagation polar decoder code length compatible

来源：评论

学校读者我要写书评

暂无评论

A 506 Gbit/s polar Successive Cancellation List decoder with CRC 31

A 506 Gbit/s Polar Successive Cancellation List Decoder with...

引用

31st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE PIMRC)

作者： Kestel, Claus Johannsen, Lucas Griebel, Oliver Jimenez, Jhon Vogt, Timo Lehnigk-Emden, Timo Wehn, Norbert Univ Kaiserslautern D-67663 Kaiserslautern Germany Koblenz Univ Appl Sci D-56075 Koblenz Germany Creonic GmbH D-67663 Kaiserslautern Germany

ISBN: (纸本)9781728144900

polar codes have recently attracted significant attention due to their excellent error-correction capabilities. However, efficient decoding of polar codes for high throughput is very challenging. Beyond 5G, data rates towards 1 Tbit/s are expected. Low complexity decoding algorithms like Successive Cancellation (SC) decoding enable such high throughput but suffer on error-correction performance. polar Successive Cancellation List (SCL) decoders, with and without Cyclic Redundancy Check (CRC), exhibit a much better error-correction but imply higher implementation cost. In this paper we in-depth investigate and quantify various trade-offs of these decoding algorithms with respect to error-correction capability and implementation costs in terms of area, throughput and energy efficiency in a 28nm CMOS FD-SOI technology. We present a framework that automatically generates decoder architectures for throughputs beyond 100 Gbit/s. This framework includes various architectural optimizations for SCL decoders that go beyond State-of-the-Art. We demonstrate a 506 Gbit/s SCL decoder with CRC that was generated by this framework.

关键词： polar Code polar decoder High Throughput 28nm List Decoding CRC Advanced Sorting Beyond 5G

来源：评论

学校读者我要写书评

暂无评论

Hardware Efficient Successive-Cancellation polar decoders Using Approximate Computing

引用

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 189-200页

作者： Yan, Chenggang Cui, Yuxuan Chen, Ke Wu, Bi Liu, Weiqiang Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 211106 Peoples R China

Benefiting for its capacity-achieving property, the polar codes have attracted wide attention in various forward error correction (FEC) codes. Although Successive-Cancellation (SC) decoders have low hardware complexity, their limited thoughput leads to low hardware efficiency. In this paper, two novel processing elements (PE) units for SC decoders are proposed by the reconstruction of key functions. Approximate comparator and adder-subtractor are developed in the proposed PEs to further enhance the hardware efficiency of the SC decoders with neglectable bit error rate (BER) performance degradation. The designs are implemented and evaluated on 28nm CMOS technology. Simulation results indicate that the area efficiency of two designs are 17.758r Gb/s/mm(2) and 14.416r Gb/s/mm(2) with 1024-bit code length and the code rate r, which are 26.7% and 9.7% better than the state-of-the-art SC implementations. Moreover, the low complexity Fast Simplified SC (Fast-SSC) decoder implemented with proposed approximate PEs has 60.3% area efficiency improvement than the prior Fast-SSC decoders with equivalent BER performance.

关键词： polar decoder successive-cancellation (SC) approximate PE units hardware efficiency image transmission

来源：评论

学校读者我要写书评

暂无评论

Generation of Efficient Self-adaptive Hardware polar decoders Using High-Level Synthesis 33

Generation of Efficient Self-adaptive Hardware Polar Decoder...

引用

33rd IEEE International Workshop on Signal Processing Systems (IEEE SiPS)

作者： Delomier, Yann Le Gal, Bertrand Crenne, Jeremie Jego, Christophe Univ Bordeaux IMS CNRS Bordeaux INPUMR 5218 F-33400 Talence France

ISBN: (纸本)9781728119274

Recent advances in 5G digital communication standard implementations advocate for the use of polar codes for the Enhanced Mobile Broad Band (EMBB) control channels. However, in many cases, implementing efficient hardware decoder over a short duration is very challenging. Specialized knowledge is required to facilitate testing, rapid design iterations and fast prototyping. In this paper, we present a model-based design methodology to generate efficient hardware SC polar decoders from high-level synthesis tools. The abstraction level flexibility is evaluated and generated decoders architectures are compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit width, pruning level and working frequency enable high throughput decoder designs with moderate hardware complexities. Decoding throughput between 10 to 310 Mbit/s and hardware complexity between 1,000 and 21,000 LUTs are reported for the generated architectures.

关键词： polar code polar decoder FPGA HLS design space exploration

来源：评论

学校读者我要写书评

暂无评论

Deep learning-enabled polar code decoders for 5G networks and beyond

引用

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2024年 177卷

作者： Meenalakshmi, M. Chaturvedi, Saurabh Dwivedi, Vivek K. Jaypee Inst Informat Technol Dept Elect & Commun Engn Noida 201309 India

The fifth generation (5G) wireless communication standard aims to integrate multiple networks, offering high throughput, large bandwidth, and ultra-low latency. Importantly, channel coding is now a crucial component of 5G wireless communication systems. polar codes, introduced by Erdal Arikan, are linear block codes chosen for 5G control channels due to their capacity-reaching properties and efficient encoding/decoding algorithms. polar codes are expected to be vital for achieving high reliability and low latency in 6G wireless communication systems, with current research focused on enhancing polar decoders. Two main polar decoder types exist: successive cancellation (SC) with lower complexity but limited throughput, and belief propagation (BP) with higher throughput but increased complexity. Addressing these challenges, deep learning (DL) techniques enhance both SC and BP decoders, leveraging fault tolerance, parallel and distributed processing ability, scalability, and better self-learning capability. The application of the DL technique in polar decoders lowers the cost of computation and significantly enhances the decoders' performance. This paper surveys novel DL-based SC/BP polar decoder approaches, evaluating error performance, decoding competence, learning efficiency, memory requirements, and hardware complexity. The review concludes that DL-based polar decoders hold great potential for enhancing performance in 5G networks and beyond.

关键词： 5G networks polar code polar decoder Deep learning Successive cancellation Belief propagation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：