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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Xia, Kaifeng Wu, Bin Zhou, Xiaoping Xiong, Tao Chinese Acad Sci Inst Microelect Bei Jing Peoples R China

ISBN: (纸本)9781479953417

This paper presents an efficient memory-based fast Fourier transform processor including 35 different working sizes for LTE systems. A factorization method named high-radixsmall-butterfly combined with a conflict-free address scheme for 2(p)3(q)5(r) point memory-based FFT processor is proposed. The processor can not only provide conflict-free concurrent data access from different memory banks but also continuous-flow working mode. Moreover, we exploit prime factor algorithm to decrease the multiplications and twiddle factor storage. In addition, a unified Winograd Fourier transform algorithm butterfly core was designed for the small 2, 3, 4, 5-point DFTs. The FFT processor was implemented in a SMIC 55nm CMOS process with core area 1:063mm(2). The chip consumes 40.8mW at 122.88MHz operating frequency with 1.08V voltage supply.

关键词： conflict-free address scheme memory-based FFT processor prime factor algorithm Winograd algorithm LTE

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A 0.37mm² LTE/Wi-Fi Compatible, Memory-Based, Runtime-Reconfigurable 2ⁿ3^m5^k FFT Accelerator Integrated with a RISC-V Core in 16nm FinFET

A 0.37mm<SUP>2</SUP> LTE/Wi-Fi Compatible, Memory-Based, Run...

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13th IEEE Asian Solid-State Circuits Conference (A-SSCC)

作者： Wang, Angie Richards, Brian Dabbelt, Palmer Mao, Howard Bailey, Stevo Han, Jaeduk Chang, Eric Dunn, James Alon, Elad Nikolic, Borivoje Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781538631782

Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multi-standard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2(n)3(m)5(k) FFT accelerator was generated by a custom hardware generator to meet the requirements of common wireless standards (Wi-Fi, LTE). The accelerator is integrated with a RISC-V processor, and the measured 16nm FinFET chip runs up to 940MHz and consumes 0.46 to 22.6mW of power when running FFT benchmarks for Wi-Fi and LTE symbol lengths.

关键词： hardware generator runtime reconfigurability fast Fourier transform Cooley-Tukey algorithm prime factor algorithm Winograd's Fourier transform algorithm Chisel LTE Wi-Fi RISC-V

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A GENERATOR OF MEMORY-BASED, RUNTIME-RECONFIGURABLE 2^N3^M5^K FFT ENGINES 41

A GENERATOR OF MEMORY-BASED, RUNTIME-RECONFIGURABLE 2<SUP>N<...

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41st IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Wang, Angie Bachrach, Jonathan Nikolic, Borivoje Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781479999880

Runtime-reconfigurable, mixed-radix FFT/IFFT engines are essential for modern wireless communication systems. To comply with varying standards requirements, these engines are customized for each modem. The Chisel hardware construction language has been used in this work to create a generator of runtime-reconfigurable 2(n)3(m)5(k) FFT engines targeting software-defined radios (SDR) for modern communications, but with flexibility to support a wide range of applications. The generator uses a conflict-free, in-place, multi-bank SRAM design, and exploits the duality of decimation-in-frequency (DIF) and decimation-in-time (DIT) FFTs to support continuous data flow with only 2N memory blocks. DFT decomposition using the prime-factor algorithm (PFA) followed by the Cooley-Tukey algorithm (CTA) reduces twiddle ROM sizes. A programmable Winograd's Fourier Transform (WFTA) butterfly supporting radix-2/3/4/5/7 operations reuses radix-7 hardware to support reconfigurability with minimal area penalty. The generated FFTs use 50% less memory than iterative FFTs from Spiral. The twiddle ROM size of the generated LTE/WiFi FFT engine is 16% smaller than that of a 2048-pt Spiral design.

关键词： Fast Fourier Transform Cooley-Tukey Winograd's Fourier Transform prime factor algorithm Reconfigurable Hardware Generator

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An efficient prime factor memory-based FFT processor for LTE systems

An efficient prime factor memory-based FFT processor for LTE...

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International Symposium on Circuits and Systems

作者： Kaifeng Xia Bin Wu Xiaoping Zhou Tao Xiong Institute of Microelectronics of Chinese Academy of Sciences Bei-jing China

ISBN: (纸本)9781479953424

Abstract: This paper presents an efficient memory-based fast Fourier transform processor including 35 different working sizes for LTE systems. A factorization method named high-radix-small-butterfly combined with a conflict-free address scheme for 2~p3~q5~r point memory-based FFT processor is proposed. The processor can not only provide conflict-free concurrent data access from different memory banks but also continuous-flow working mode. Moreover, we exploit prime factor algorithm to decrease the multiplications and twiddle factor storage. In addition, a unified Winograd Fourier transform algorithm butterfly core was designed for the small 2, 3, 4, 5-point DFTs. The FFT processor was implemented in a SMIC 55nm CMOS process with core area 1.063mm~2. The chip consumes 40 8mW at 122.88MHz operating frequency with 1.08V voltage supply.

关键词： LTE conflict-free address scheme memory-based FFT processor prime factor algorithm Winograd algorithm

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Self-calibration of divided circles on the basis of a prime factor algorithm

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MEASUREMENT SCIENCE AND TECHNOLOGY 2008年第1期19卷 015101 (11-015101 (11页

作者： Probst, R. Phys Tech Bundesanstalt D-38116 Braunschweig Germany

A new method for the self-calibration of divided circles is presented which is based on a known prime factor algorithm for the discrete Fourier transform (DFT). The method, called prime factor division (PFD) calibration, is of interest in angle metrology specially for self-calibrating angle encoders, and generally for a significant shortening of the cross-calibration between two divided circles. It requires that the circular division number N can be expressed as a product N = R x S, whereby the factors R and S are relatively prime integer numbers. For the self-calibration of a divided circle, N difference measurements between R angle positions in a regular distribution and one reference angle position determined by S are evaluated by a two-dimensional DFT, yielding the N absolute division errors. The factor R is preferably chosen small, down to a minimum of R = 2, whereas the factor S may be as large as appropriate for the division number N of interest. In the case of a cross-calibration between two divided circles, the PFD method reduces the number of measurements necessary from N-2 to (R + 1) x N. Experimental results are demonstrated for the calibrations of an optical polygon with 24 faces (prime factor product 3 x 8) and a gearwheel with 44 teeth (prime factor product 4 x 11).

关键词： self-calibration divided circles circular division angle encoder angle measurement prime factor algorithm discrete Fourier transform metrology

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Double factors algorithm for Computing DFT

Double Factors Algorithm for Computing DFT

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International Symposium on Image Analysis and Signal Processing

作者： Li, Haijun Yang, Caojun Peng, Wenbiao China Three Gorge Univ Elect & Informat Coll Yichang Hubei Peoples R China

ISBN: (纸本)9781424439867

A fast Fourier transform algorithm for computing N=N(1)xN(2)-point DFT, where both factors N-1 and N-2 are smaller positive integer, said to be a double factors algorithm(DFA), is developed. The DFA subdivides a DFT of length N=N(1)xN(2) into smaller transforms of length N-1 and N-2 and takes the following steps:(1) computes N1N2-point DFTs, (2) multiplies the values of DFT by twiddle factors, (3) computes N2N1-point DFTs. The structure of the DFA is similar to those of the most simple PFA and WFTA, but N-1 and N-2 are not necessarily relatively prime. When N=2(M) or 4(M), the total number of computations of DFT in the DFA is less than those in the radix-2 and radix-4 FFT algorithm but slightly more than that in the split-radix FFT algorithm. When N is other values, the total number of computations of DFT in the DFA is less than those in the PFA and WFTA.

关键词： double factors algorithm prime factor algorithm radix-4 FFT splix-radix FFT smaller-length DFT

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Double factors algorithm for Computing DFT

Double Factors Algorithm for Computing DFT

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International Conference on Image Analysis and Signal Processing

作者： Haijun Li Caojun Yan Wenbiao Peng Electrical and Information College China Three Gorge University

ISBN: (纸本)9781424439874

A fast Fourier transform algorithm for computing N=N_1×N_2-point DFT, where both factors N_1 and N_2 are smaller positive integer, said to be a double factors algorithm (DFA), is developed. The DFA subdivides a DFT of length N=N_1×N_2 into smaller transforms of length N_1 and N_2 and takes the following steps:(1) computes N_1 N_2-point DFTs, (2) multiplies the values of DFT by twiddle factors, (3) computes N_2 N_1-point DFTs. The structure of the DFA is similar to those of the most simple PFA and WFTA, but N_1 and N_2 are not necessarily relatively prime. When N=2~M or 4~M, the total number of computations of DFT in the DFA is less than those in the radix-2 and radix-4 FFT algorithm but slightly more than that in the split-radix FFT algorithm. When N is other values, the total number of computations of DFT in the DFA is less than those in the PFA and WFTA.

关键词： Double factors algorithm prime factor algorithm Radix-4 FFT Splix-radix FFT Smaller-length DFT DELAYED FLAP APPROACH Doped fiber amplifiers Deferoxamine discrete Fourier transform FFT algorithm Fly ash

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Multiplierless Winograd and prime factor FFT implementation

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IEEE SIGNAL PROCESSING LETTERS 2004年第9期11卷 740-743页

作者： Macleod, MD Univ Cambridge Dept Engn Cambridge CB2 1PZ England

This letter describes fixed-point implementations of the Winograd and prime factor FFT algorithms in which multiplications are replaced by additions, subtractions and shifts. Methods are described for minimizing the number of additions and subtractions, while achieving a required level of accuracy. VLSI implementation of the resulting FFTs could achieve very high speed and/or power efficiency. The method can be used to provide any chosen accuracy;examples are presented for 12 to 20 bit accuracy.

关键词： fast algorithms Fourier transforms prime factor algorithm VLSI hardware winograd DFT

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prime factor algorithm for multidimensional discrete cosine transform

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2001年第9期49卷 2156-2161页

作者： Bi, G Zeng, YH Chen, YQ Nanyang Technol Univ Sch Elect & Elect Engn Singapore 2263 Singapore

A prime-factor fast algorithm is proposed for the computation of the multidimensional forward and inverse discrete cosine transform (DCT). By using an example of two-dimensional (2-D) DCT, it shows that an r-dimensional DCT can be obtained from a 2r dimensional DCT with a post-processing stage. Efficient method for input/output mapping is reported to substantially reduce the computational overhead associated with the prime-factor algorithm.

关键词： discrete cosine transform prime factor algorithm

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Efficient prime factor algorithm and address generation techniques for the discrete cosine transform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 2001年第10期48卷 985-988页

作者： Chau, LP Lun, DPK Siu, WC Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

This brief proposes an efficient prime factor algorithm for the discrete cosine transform. In the proposal, we formulate the decomposition directly, by using the proposed input and output mapping, a novel in-place address generation scheme for input index mapping is derived, while the formulations in the literature require a table to store the index mapping. Besides, our approach requires one output index mapping only while the conventional algorithms require two index mapping. Hence, by using the proposed mappings and address generation techniques, less temporary storage is required, such that a reduction on memory requirement can be achieved during the implementation. A comparison of the address generation time between our approach and the conventional approach is also shown.

关键词： address generation technique discrete cosine transform fast algorithm prime factor algorithm

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