检索结果-内蒙古大学图书馆

Reversible priority encoder in quantum-dot cellular automata

INORGANIC CHEMISTRY COMMUNICATIONS 2024年 164卷

作者： Heikalabad, Saeed Rasouli Islamic Azad Univ Ind Nanotechnol Res Ctr Tabriz Branch Tabriz Iran

This paper presents a reversible structure for priority encoder. In order to expand the proposed design, the proposed structure is presented based on a modular method. For this purpose, first using the feature of insignificance of least-significant inputs when the value of most-significant input is one in the priority encoder, a special purpose reversible OR gate is introduced. Then, using this gate, we provide a reversible structure for the 4: 2 priority encoder. The proposed structure is designed entirely with reversible OR gates and inverter gates. We design the cell layout of this structure in QCADesigner software. In order to prove the modularity of the proposed design, the structure of 8: 3 reversible priority encoder is designed using 4: 2 reversible priority encoder.

关键词： Quantum-dot cellular automata Nanotechnology Modular Reversible priority encoder

来源：评论

学校读者我要写书评

暂无评论

Architectural analysis of 1-D to 2-D array conversion of priority encoder

引用

INTERNATIONAL JOURNAL OF SYSTEM ASSURANCE ENGINEERING AND MANAGEMENT 2023年第5期14卷 1726-1737页

作者： Mishra, Alok Kumar Anand, Shail Singh, Nishant Dhandapani, Vaithiyanathan Kaur, Baljit Natl Inst Technol Delhi Dept Elect & Commun Engn Delhi 110040 India

In this paper, a high-performance priority encoder of the 2-dimensional array is investigated and modified. This work involves 64-bit priority encoder design and verification using Verilog and cadence virtuoso. For the Verilog code, Vivado has been used for the Artix-7 FPGA board. For Cadence virtuoso, GPDK 180 nm CMOS technology has been used. By using a reduced 2-D priority encoder, 1000 transistors have been saved. Due to this, the delay of the whole 64-bit priority encoder is reduced by 62.17% as compared to PE64 and 61.68% as compared to modified PE64.

关键词： High performance priority encoder Artix-7 FPGA Multiplexer

来源：评论

学校读者我要写书评

暂无评论

Optimizing Hardware Resources: A Study on Power, and Temperature in priority encoder 5

Optimizing Hardware Resources: A Study on Power, and Tempera...

引用

5th International Conference on Smart Electronics and Communication, ICOSEC 2024

作者： Singh, Gurdeep Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798331504403

This study presents a novel method for building an energy-efficient priority encoder-more especially, for FPGA families-that is based on Energy optimization is sometimes disregarded in conventional systems even if it is a fundamental part of encoder designs, particularly in cases of restricted power. Leveraging the unique characteristics of FPGA, optimize topologies to lower power consumption without sacrificing speed or capability using comprehensive synthesis and simulations. This paper validates the efficiency of the approach in generating appreciable power reductions without compromising performance. This discovery not only advances FPGA-based circuit development but also energy savings in many other fields. Among the other factors we have measured are the thermal margin of the Kintex board- 72.7 degrees Celsius-and the board's total power consumed-1.32 W. © 2024 IEEE.

关键词： Energy efficient FPGA (Field-Programmable Gate Array) Kintex Power saving priority encoder Temperature Vivado W (Watt) Xilinx

来源：评论

学校读者我要写书评

暂无评论

Leveraging a Novel Two-Level priority encoder for High-Precision Integer Multiplication 66

Leveraging a Novel Two-Level Priority Encoder for High-Preci...

引用

2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

作者： Phillips, Maxwell Hassan, Firas Ammar, Ahmed Hagerdorn, Nathan Ohio Northern University Department of Electrical and Computer Engineering and Computer Science AdaOH United States

ISBN: (纸本)9798350302103

High-precision integer multiplication is critical for applications in physics, mathematics, and most importantly, encryption. Existing multiplication algorithms must process every bit of the multiplier, resulting in high hardware complexity and latency. To improve upon this, we propose an integer multiplication algorithm that must only process the high bits of the multiplier. This algorithm improves shift-and-add multiplication by leveraging a novel two-level structure for a priority encoder, decoder, and barrel shifter. Each component splits inputs into coarse and fine sections and processes each separately, simplifying the hardware design. The proposed algorithm takes sign and magnitude inputs, but could be extended to allow streamlined processing of two's complement inputs. We implemented the algorithm on an FPGA device using multiple clocks to allow rapid input of high-precision data over a serial connection and to optimize multiplication speed. By processing only high bits, the average performance of the proposed algorithm is doubled compared to the traditional shift-and-add algorithm. Additionally, our algorithm increases performance significantly for sparse inputs with few high bits. Overall, our algorithm outperforms existing methods in the best case, surpasses or matches other methods in the average case, and performs no worse than the traditional method in the worst case. © 2023 IEEE.

关键词： encryption high precision integer multiplication priority encoder variable radix

来源：评论

学校读者我要写书评

暂无评论

Analysis of all-optical priority encoder using plasmonics waveguide

引用

JOURNAL OF COMPUTATIONAL ELECTRONICS 2021年第5期20卷 1884-1890页

作者： Karki, Bhishma Pal, Amrindra Sharma, Sandeep Tribhuvan Univ Dept Phys Trichandra Multiple Campus Kathmandu 44600 Nepal DIT Univ EECE Dept Photon Lab Dehra Dun 248009 Uttarakhand India OMKARR Tech New Delhi India iNurture Educ Solut Bengaluru Karnataka India Ajeenkya DY Patil Univ Dept IT Pune Maharashtra India

The proposed all-optical circuit utilizes the deep sub-wavelength confinement properties of plasmonic metal-insulator-metal waveguides. All-optical priority encoder accepts 2(n) outputs. The priority encoder is designed using the plasmonics waveguide-based Mach-Zehnder interferometer (P-MZI). The P-MZI works as an all-optical switch. The switching of the signal depends on the power of the applied optical input signal. This waveguide has a nonlinear material inside. The proposed work is analyzed using the finite-difference time-domain method, and a mathematical description is also given. Parameters such as insertion loss and extinction ratio are reported as 15.82 dB and 0.57 dB, respectively.

关键词： priority encoder Finite-difference time-domain method Plasmonic Nonlinear material

来源：评论

学校读者我要写书评

暂无评论

Design and simulation of an all-optical priority encoder based on 2-D photonic crystal

引用

OPTICAL AND QUANTUM ELECTRONICS 2023年第4期55卷 314-314页

作者： Talebzadeh, Reza Nasab, Aziz-Morad Vali Moayed, Seyed Hossein Lorestan Univ Khorramabad Lorestan Iran Tech & Vocat Univ TVU Dept Elect & Comp Engn Tehran Iran

In this paper, we designed and simulated an all-optical priority encoder based on the photonic crystal. For this purpose, we have used the interference of optical waves inside the waveguides. The proposed structure is very simple and compact so that the photonic crystal lattice consists of only 29 x 27 dielectric rods with radii of 102.9 nm in the square arrangement. The lattice constant and area of the structure are 490 nm and 178 mu m(2), respectively. First, we created input and output waveguides in the structure. After that, by imposing some point defects, we have controlled the behavior of light. The results of the time analysis show that the average time delay of the proposed structure is less than 1.2 ps and hence is very fast.

关键词： Photonic crystal priority encoder All-optical gate Waveguide

来源：评论

学校读者我要写书评

暂无评论

High-Precision priority encoder Based Integer Division Algorithm

High-Precision Priority Encoder Based Integer Division Algor...

引用

IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Ammar, Ahmed Drennen, Hayden Hassan, Firas Ohio Northern Univ ECCS Dept Ada OH 45810 USA

ISBN: (纸本)9781665424615

In the past years, the demand for high-precision arithmetic has significantly increased, which raised the need for devices that can handle high-precision computations. Therefore, in this paper, we propose a hardware for high-precision division. The proposed hardware is implemented for 1024 bits, and it can be easily extended to larger bits. The hardware performs division on integer numbers represented in sign and magnitude, and produces quotient and remainder. A priority encoder is used to improve the convergence rate, and to make the dividend and divisor lengths not required as inputs. To reduce complexity, most of the components were implemented in two levels. We provide an upper limit and a closed-form expression for the convergence rate. We synthesized the hardware on a Field-Programmable Gate Array (FPGA) device. We simulated the hardware at the bit level in Matlab using Monte Carlo simulations. We also simulated the hardware in ModelSim. Compared to the existing approaches, the results show that for 64-bit division, our hardware reduces the number of LUTs and slices by 18.4% and 67.5%, respectively, and improves delay by 50.3 degrees A. As for 256-bit division, our hardware reduces the number of slices by 60.7% and improves delay by 33.25%, however, it increases the number of LUTs by 11.32%.

关键词： Integer division hardware implementation priority encoder high-precision

来源：评论

学校读者我要写书评

暂无评论

A novel proposal for all optical priority encoder using photonic crystal based nonlinear cavities

引用

OPTICAL AND QUANTUM ELECTRONICS 2022年第7期54卷 415-415页

作者： Tan, Hanhong Serajmohammadi, Somaye Guangdong Univ Sci & Technol Sch Mech & Elect Engn Dongguan 523083 Guangdong Peoples R China Espandar Cement Investment Co Tech & Engn Dept Tehran Iran

Three kinds of nonlinear ring resonators were used for designing an all optical encoder based on photonic crystals. The simulation results show that when more than one input port is active the priority is with the highest order input port. Therefore the proposed structure can serve as an all optical photonic crystal based priority encoder. The rise time for the proposed structure is 1 ps.

关键词： Photonic Crystal Nonlinear cavity Kerr effect priority encoder

来源：评论

学校读者我要写书评

暂无评论

Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design

引用

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 2021年第3期34卷 e2850-e2850页

作者： Kaity, Aishwarya Singh, Sangeeta Hossain, Kabirul Natl Inst Technol Patna Microelect & VLSI Design Lab Patna Bihar India Ctr Dev Adv Comp Dept Res & Dev Kolkata India

The transistorless technology, quantum dot cellular automata (QCA) becomes one of the potential candidates of nanotechnology for signal processing circuits because of its ultra-low power requirement, high frequency of operation, extreme-low area requirement, and short channel effect (SCEs) immune at nanoscale circuits. Quasi-adiabatic switching of QCA makes its data transfer faster. This work reports faster, smaller, and low-power, 4-to-2 and 8-to-3 encoder, and priority encoder circuits designed on QCA platform. Both of these encoders and priority encoders are widely used circuits for communication to encode the data. These circuits are realized using three-input majority gates, five-input majority gates, and co-planar clock zone-based crossover technique. The proposed circuits show the improvement in performance in terms of cell count, area requirement, delay, quantum cost, and energy dissipation as compared to the existing circuits. The cell count and the area requirement of the proposed circuits have been magnificently lowered as compared to the recent literature. Moreover, these circuits also require 75% lesser clock periods than the existing literature, thus demonstrate lower latency. This work shows the way for future exploration of QCA-based encoder circuits.

关键词： coplanar crossover encoder majority gate priority encoder quantum‐ dot cellular automata quasi‐ adiabatic switching

来源：评论

学校读者我要写书评

暂无评论

QCA based priority encoder using Toffoli gate 14

QCA based Priority Encoder using Toffoli gate

引用

14th IEEE International Conference on Application of Information and Communication Technologies (AICT)

作者： Safoev, Nuriddin Abdukhalil, Ganiev Abdisalomovich, Karimov Abduqodir Tashkent Univ Informat Technol Dept Providing Informat Secur Tashkent Uzbekistan

ISBN: (纸本)9781728173863

This paper presents a design of a reversible priority encoder that is an important element for encoding and decoding addresses. Promising nanotechnology, Quantum-dot Cellular Automata (QCA), is a possible platform for implementing reversible circuits. In this paper, a reversible 4 to 2 priority encoder architecture is proposed with low complexity on the QCA platform. In order to implement a reversible encoder circuit, the low-cost design of the Toffoli gate is proposed. Structural analysis using the QCADesigner simulation tool is carried out to evaluate the proposed designs.

关键词： priority encoder Toffoli gate QCA reversible circuit power dissipation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：