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Designing and Implementing a Fault-Tolerant priority encoder in QCA Nanotechnology

ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY 2021年第6期10卷

作者： Salimzadeh, Fereshteh Safarpoor, Elahe Heikalabad, Saeed Rasouli Islamic Azad Univ Ind Nanotechnol Res Ctr Tabriz Branch Tabriz Iran Islamic Azad Univ Dept Comp Engn Tabriz Branch Tabriz Iran

The quantum-dot cellular automata (QCA) is a new and impressive nano-technology for implementing electronic circuits at nanoscale. This nanotechnology is more impressive than CMOS technology in terms of higher speed, smaller area and less energy consumption, and can make significant progress in the design of logic circuits. quantum-dot cellular automata circuits are likely to have various defects during fabrication. In fabrication process, some different defects might be occurred (like cell deletion, cell addition, cell displacement, cell rotation, and misalignment). That's why researchers are eager to design fault-tolerant circuits. In this paper, a fault-tolerant priority encoder is designed. For this purpose, a new fault tolerant majority gate is provided first. The results of simulations are shown with the QCADesigner software V2.0.3. The simulation results indicate an improvement in the performance of the proposed structure.

关键词： Quantum Cellular Automata technology priority encoder Fault-Tolerance Nanotechnology

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A 32-bit Integer Division Algorithm Based on priority encoder 27

A 32-bit Integer Division Algorithm Based on Priority Encode...

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27th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS)

作者： Hassan, Firas Ammar, Ahmed Drennen, Hayden Ohio Northern Univ ECCS Dept Ada OH 45810 USA

ISBN: (纸本)9781728160443

In this paper, an algorithm for 32-bit integer division is proposed. The algorithm calculates the integer division of positive and negative dividends and divisors represented in sign and magnitude. It calculates the magnitudes and signs of the quotient and remainder separately based on the magnitudes and signs of the divided and divisor. In the algorithm, the magnitude of the remainder is initially set to be the dividend and is iteratively reduced until it becomes smaller than the magnitude of the divisor;afterwards the algorithm converges. A priority encoder is used to improve the convergence rate by skipping the zeros between the high bits while shifting the divisor in each iteration to be aligned with the partial remainder. The magnitude of the quotient is initially set to zero and updated based on the amount of shift in each iteration. A hardware architecture is proposed to implement the algorithm. The hardware is synthesized on an FPGA device, and its functionality was verified by ModelSim simulations. The results show that the hardware achieves a maximum operating frequency of 90.9MHz, and achieves an improvement of 31.43%, 59.12%, and 18.1%, in terms of delay, LUTs, and slices, respectively, over the most recent existing approach. MATLAB simulations were also conducted to measure the convergence rate. The MATLAB simulation results show that on average the convergences rate is less than or equal to the half of the difference between the number of bits in the dividend and the number of bits in the divisor.

关键词： Integer division hardware implementation priority encoder

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Novel design of reversible priority encoder in quantum dot cellular automata based on Toffoli gate and Feynman gate

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JOURNAL OF SUPERCOMPUTING 2019年第10期75卷 6882-6903页

作者： Das, Jadav Chandra De, Debashis Swami Vivekananda Inst Sci & Technol Dept Comp Sci & Engn Kolkata 700145 India West Bengal Univ Technol Dept Comp Sci & Engn BF 142Sect 1 Kolkata 700064 India Univ Western Australia Dept Phys Crawley WA 6009 Australia

In accordance with Moore's law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

关键词： QCA Majority logic Reversible gate Feynman gate Toffoli gate priority encoder

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A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS

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MICROPROCESSORS AND MICROSYSTEMS 2020年第0期73卷 102970-000页

作者： Xuan-Thuan Nguyen Trong-Thuc Hoang Hong-Thu Nguyen Inoue, Katsumi Pham, Cong-Kha Univ Toronto Toronto ON Canada Univ Electrocommun Tokyo Japan

Although priority encoder (PE) plays a vital role in many applications, they perform poorly with large-sized input data. Our previous work tackles this problem by introducing a so-called one-dimensional-array to two-dimensional-array (1D-to-2D) conversion method, which can effectively handle up to a 4,096-bit PE. Taking advantage of the previous achievement, this paper further explores the benefit of a 1D-to-2D-based multi-match priority encoder (MPE). Specifically, compared with other designs implemented in ASlC and FPGA, the proposed PE and MPE outperformed by 4.4 times and 1.7 times, respectively. A 256-bit MPE chip fabricated in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process was also reported. The measurements showed that at 0.9-V supply voltage, the chip was fully operational at 50 MHz and consumed approximately 140.3 mu W. More significantly, by exploiting the clock-gating and reverse back-gate biasing techniques, the standby leakage current at 0.6 V dropped to 1.12 nA, which is equivalent to the 0.67-nW standby leakage power. (C) 2020 Elsevier B.V. All rights reserved.

关键词： priority encoder Multi-match priority encoder 1D-to-2D Standby power High performance 65 nm SOTB Silicon on thin buried oxide ASIC FPCA

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Low power high performance priority encoder using 2D-array to 3D-array conversion

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Procedia Computer Science 2020年 171卷 1037-1045页

作者： K Anil Chandra N S Murty Dept of Electronics & Communication engineering Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

This paper discusses priority encoder and its designing complexity for higher number of input bits, i.e., 64, 128, 256, and so on. In order to reduce the complexity and power consumption of the circuit, a new circuit with three-directional (3D) array priority encoder is introduced. This 3D-array priority encoder circuit reduces the power consumption by 23.908 % and the transistors count by 19.572 % using 180nm technology, by using 45nm technology power consumption is reduced by 23.588% and transistors count remains same when compared to the existing two-directional (2D) array priority encoder. In this paper 64-bit input priority encoder is implemented using Cadence Virtuoso GPDK-180 nm and 45nm technology.

关键词： priority encoder critical path power delay product GPDK-180nm 45nm technology power consumption transistors

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A Scalable VHDL-Implementation Technique of the priority encoder Structure into FPGA 38

A Scalable VHDL-Implementation Technique of the Priority Enc...

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IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO)

作者： Yershov, Roman D. CNUT Ind Elect Dept Chernihiv Ukraine

ISBN: (纸本)9781538663837

The problem of scalable and optimal behavior-style description of the priority encoder into FPGA was examined. The structural synthesis technique of a scalable priority resolving circuits in sequential and parallel forms, which allow improving the FPGA resource utilization in comparison with typical description, was proposed. A novel approach of scalable synthesis of the triangular threshold-logic gate array was also proposed. The results of research and development, which have presented by structure generation circuit and algorithm, were confirmed by correct register-transfer level representation and during timing simulation. The numeric comparative assessments of FPGA recourses utilizing depending both the encoder inputs number, priority resolving circuit topology and threshold-logic gate unit was implemented.

关键词： VHDL FPGA daisy-chain priority encoder structural synthesis multiple match resolver regular structure scalable design generic logic element

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Design and Analysis of priority encoder with Low Power MTCMOS Technique 8

Design and Analysis of Priority Encoder with Low Power MTCMO...

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8th IEEE International Conference on Cloud Computing, Data Science and Engineering (Confluence) / Global Technology, Innovation and Enterpreneurship Summit

作者： Saini, Sakshi Singh, Balwinder Pahuja, Hitesh Chhabra, Varun A. Ctr Dev Adv Comp Mohali Acad Consultancy & Serv Div Sahibzada Ajit Singh Nag India

ISBN: (纸本)9781538617199

In recent trends power optimization is becoming one of the most important factor in integrated circuits today. Low power MTCMOS technique has appeared as an encouraging technique to decrease power dissipation, leakage currents and leakage power. High performance priority encoder was designed using MTCMOS technique and compared with conventional CMOS technique. Comparative analysis showed that how these techniques were used to optimize the average power and shows significant improvement in terms of speed. After the comparative analysis, it has been concluded that as compared to the conventional design, MTCMOS technique reduced power by 37% at 90nm and 21% at 45nm. Leakage current is reduced to 54% at 90nm and 96% at 45nm. Moreover, energy consumption was also reduced to 32% at 90nm and 20% at 45nm. This paper addresses remarkable uses of low power techniques in high speed digital circuits, mobile phones and high operating frequencies.

关键词： priority encoder CMOS MTCMOS Power Dissipation Power Delay Product Leakage Currents

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Monoimmittance priority encoder

Monoimmittance priority encoder

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SPIE-IEEE-PSP WILGA on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments

作者： Bilynsky, Yosyp Y. Stakhova, Volodymyr P. Lazarev, Alexander A. Smolarz, Andrzej Azeshova, Zhanar Vinnytsia Natl Tech Univ 95 Khmelnitsky Shose Str UA-21021 Vinnytsia Ukraine Lublin Univ Technol Nadbystrzycka 38A PL-20618 Lublin Poland Kazakh Natl Res Tech Univ Alma Ata Kazakhstan

ISBN: (数字)9781510622043

ISBN: (纸本)9781510622043

The work is devoted to the development of an eight-digit priority encoder constructed on monoimmittance logic gates. The electric circuit on the properties of the long lines in the microwave range was developed. The mathematical model and additional optimization were carried out. The monoimmittance priority encoder computer simulation was performed. The advantages of the developed monoimmittance priority encoder are increased speed, simplicity of design, passive power supply, absence of a threshold of minimum operating voltage and increased immunity to electromagnetic interferences.

关键词： monoimmittance logic gate combinational logic priority encoder passive digital components microwave computing devices

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priority encoder using reversible logic gates in QCA 8

Priority Encoder using reversible logic gates in QCA

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8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)

作者： Sen, Riya Das, Sandip Mazumder, Gitika Guha Yadav, Priyanka Neogy, Ballary Pandey, Rohit Sharma, Shalu Jana, Biswajit Univ Engn & Management Elect & Commun Engn Jaipur Rajasthan India

ISBN: (纸本)9781538633717

Reversible logic gate has gained importance in recent times due to its low power dissipation and less information loss. QCA on the other hand has low power consumption and has applications in reversible logic. In this paper, a 4x2 priority encoder is proposed which is based on reversible logic implemented in QCA. Firstly, this paper discusses about QCA layout design of Fredkin gate and Universal Reversible Logic Gate (URLG). Secondly, this paper uses reversible logic gate (both Fredkin and URLG) to design a 4x2 priority encoder in QCA.

关键词： Reversible logic Fredkin gate URLG QCA priority encoder

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A Scalable High-Performance priority encoder Using 1D-Array to 2D-Array Conversion

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2017年第9期64卷 1102-1106页

作者： Xuan-Thuan Nguyen Hong-Thu Nguyen Cong-Kha Pham Univ Electrocommun Dept Engn Sci Tokyo 1828585 Japan

In our prior study of an L-bit priority encoder (PE), a so-called one-directional-array to two-directional-array conversion method is deployed to turn an L-bit input data into an M x N-bit matrix. Following this, an N-bit PE and an M-bit PE are employed to obtain a row index and column index. From those, the highest priority bit of L-bit input data is achieved. This brief extends our previous work to construct a scalable architecture of high-performance large-sized PEs. An optimum pair of (M, N) and look-ahead signal are proposed to improve the overall PE performance significantly. The evaluation is achieved by implementing a variety of PEs whose L varies from 4-bit to 4096-bit in 180-nm CMOS technology. According to post-placeand-route simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times, 1.5 times, and 1.4 times, as high as state-of-the-art ones.

关键词： priority encoder scalable high-performance 180 nm CMOS VLSI 1D-to-2D conversion

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