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53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

作者： Huang, Shao-Wei Chang, Yen-Jen Natl Chung Hsing Univ Dept Comp Sci & Engn Taichung 40227 Taiwan

ISBN: (纸本)9781424477739

In this paper, we present an enhanced priority encoder, called full parallel priority encoder (FPPE) that can be used in the comparator circuitry. Because there is no serial NAND-type path, the performance of FPPE is better than that of the conventional priority encoder. The comparator with FPPE is implemented in UMC 90nm CMOS technology. The simulation results show that the proposed design is 40% and 12% faster than the comparator based on NAND-type priority encoder and the comparator based on parallel MSB checking comparison, respectively.

关键词： CMOS dynamic circuit Comparator priority encoder

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Logic architecture for 2-select Arbiter using Duel Pointer 35

Logic architecture for 2-select Arbiter using Duel Pointer

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IEEE Region 10 Conference

作者： Kalpande, Mahesh D. Vyas, Vibha Coll Engn Pune Dept Elect Engn Pune Maharashtra India

ISBN: (纸本)9781479986415

Arbitration among various clients, requesting multiple resources simultaneously in high throughput system, needs multiple requests selection in single cycle. A new technique for implementation of arbiter, which selects up to two active request is proposed in this paper. 2 selector circuits are designed by modification of existing parallel prefix tree structures for architecture. Design maintains fairness among active requests by updating pointers according to grant selection algorithm presented. Simulation of design and comparison with previously work is done in terms of area and timing results.

关键词： Arbiter Parallel Prefix Tree 2 selector Round Robin Method priority encoder

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Design and Realization of General Matrix Keyboard based on STM32 2

Design and Realization of General Matrix Keyboard based on S...

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2nd International Conference on Systems and Informatics (ICSAI)

作者： Shi, Kai Wang, Zhanquan Luo, Fei Gu, Chunhua East China Univ Sci & Technol Inst Informat Sci & Engn Shanghai Peoples R China

ISBN: (纸本)9781479954582

The matrix keyboard is taken as the basic input device of MCU or embedded systems. For traditional matrix keyboard, the number of interface signal lines connected to the MCU will rapidly increase with the rise of the number of keys. And it uses row scanning to get key values in software. But this situation is not suitable for MCU (Micro-programmed Control Unit) or embedded chips which have limited hardware resources, especially in the application with human-computer interaction. A novel scheme of general matrix keyboard based on set mapping theory is proposed in this paper. It uses the combination of external interrupt and priority encoder to overcome the problems in the traditional matrix keyboard. The design details of the hardware and software are presented. Through the application in the interactive display board system, it shows that the proposed scheme is feasible and effective.

关键词： general matrix keyboard external interrupt priority encoder the interactive display system STM32

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Building Optimized Packet Filters with COFFi 22

Building Optimized Packet Filters with COFFi

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22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines ((FCCM)

作者： Hager, Sven Winkler, Frank Scheuermann, Bjoern Reinhardt, Klaus Humboldt Univ Comp Engn Grp Berlin Germany

ISBN: (纸本)9781479951116

any companies and institutions employ packet filter firewalls in order to effectively regulate network traffic. Unfortunately, the constant growth of network bandwidth makes the task of matching packet headers against potentially large rulesets more difficult, and prohibits the sole use of entirely software-based firewalls which cannot cope with such huge amounts of traffic. Instead, high-speed firewalls are often implemented in ASICs which offer a high degree of parallelism, many opportunities for operation pipelining, and low-latency access to network data. However, due to their static nature, ASICs must provide generic filtering circuitry that is hardly able to take full advantage of firewall ruleset properties, thus leading to a waste of hardware resources. Therefore, we propose a methodology to automatically compile stateless firewall rulesets to efficient circuit descriptions in synthesizable VHDL format which can be deployed in FPGA devices. The generated filtering circuitry matches incoming packet header fields against each firewall rule in parallel and leverages a pipelined design which allows for a TCAM-like deterministic classification throughput of one packet header per clock cycle. The employed matching logic is tailored to the checks specified by the translated rules and thus compact. Furthermore, the structure of the generated circuits allows for inter-rule optimizations that are performed during logic minimization. During this process, redundant hardware representations of checks that are shared between multiple rules are removed. As opposed to previous works in this domain, we exploit the structure of the given ruleset in order to aggregate the independent match results in a priority encoder of logarithmic depth, thereby achieving short processing latencies and low hardware resource consumption. We call this approach COFFi: Custom Optimized FPGA Firewalls.

关键词： Buildings Clocks Computers Field programmable gate arrays Hardware Pipeline processing Pipelines Circuit Generation FPGA Firewall Field programmable gate arrays firewalls (computers) Pipeline processing Timing devices Buildings pipeline Computer hardware Computers priority encoder packet filter minimisation of switching nets Ruleset packet head

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Four Bit priority Resolution Network Using Current Mode Winner Take All Circuit

Four Bit Priority Resolution Network Using Current Mode Winn...

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4th International Conference on Advances in Materials and Manufacturing (ICAMMP 2013)

作者： Cao, Wenqin Zhu, Haiyan Tu, Guoping Nanchang Univ Sch Sci Nanchang 330013 Jiangxi Peoples R China E China Jiaotong Univ Sch Mech & Elect Engn Nanchang 330013 Jiangxi Peoples R China Nanchang Univ Sch Sci Nanchang 330013 Jiangxi Peoples R China

ISBN: (纸本)9783038350156

This paper presents a new approach for making a four bit priority resolution circuit using current mode winner Take all (WTA) analog computation cells, the winner-takes-all circuit is employed to evaluate the highest input among a set of competing inputs and inhibit the others. This circuit consists of an input stage, a current mode Lazzaro's WTA circuit and an output stage consisting of current mirror and load resistor. This circuit is compact, consisting of a total of 28 transistors including the input stage, and a good linearity is observed in response. Simulation of proposed circuit is performed on cadence virtuoso software in 0.18 mu m CMOS process technology.

关键词： Current mode WTA circuit priority resolution network Prescaling input stage priority encoder

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Novel design of combinational and sequential logical structures in quantum dot cellular automata

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JOURNAL OF NANOSTRUCTURE IN CHEMISTRY 2013年第1期3卷 1-9页

作者： Ghosh, Bahniman Gupta, Shoubhik Kumari, Smriti Salimath, Akshaykumar Univ Texas Austin Microelect Res Ctr Austin TX 78758 USA Indian Inst Technol Dept Elect Engn Kanpur 208016 Uttar Pradesh India

Quantum dot cellular automata (QCA) is a emerging nanotechnology that promises smaller size and lower power consumption, with faster speed compared to the transistor-based technology. In this paper, we have proposed novel 8-into-3 bit simple encoder, 4-into-2 bit priority encoder, scan flip-flop, and pseudo-random bit sequence generator designs in QCA. These circuits are useful components for the design of many logical and functional circuits. Simulation results of the proposed QCA circuits are obtained by using the QCA designer tool. The correctness of the proposed circuits is hence confirmed.

关键词： Quantum dot cellular automata priority encoder Simple encoder Scan flip-flop Pseudo-random bit sequence generator

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Fast parallel prefix logic circuits for n2n round-robin arbitration

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MICROELECTRONICS JOURNAL 2012年第8期43卷 573-581页

作者： Ugurdag, H. Fatih Baskirt, Onur Ozyegin Univ Dept Elect & Elect Engn TR-34782 Istanbul Turkey Ericsson TR-34390 Istanbul Turkey

An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： Circuits for networking Computer arithmetic Logic synthesis priority encoder Timing optimization

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Design of Novel Quaternary encoders and Decoders

Design of Novel Quaternary Encoders and Decoders

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IEEE/OSA/IAPR International Conference on Informatics, Electronics and Vision (ICIEV)

作者： Jahangir, Ifat Das, Anindya Hasan, Masud Bangladesh Univ Engn & Technol Dept Elect & Elect Engn Dhaka 1000 Bangladesh Bangladesh Univ Engn & Technol Dept Comp Sci & Engn Dhaka 1000 Bangladesh

ISBN: (纸本)9781467311526

In this work, a novel quaternary algebra has been employed to design quaternary encoders and decoders of any size. Both priority and ordinary encoders has been designed. The priority encoder in this work may have any arbitrary permutation of input priorities;the design procedure is generic and works for any such permutation. Although no work has ever been done regarding arbitrarily large and randomly prioritized priority encoders in quaternary domain, there exist numerous reports on smaller encoders as well as decoders. The design complexity of the present work has been compared with some of such works done earlier and our designs are more favorable in terms of complexity, especially for large encoders and decoders.

关键词： Quaternary encoder priority encoder Quaternary Decoder Large encoders and Decoders

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A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2011年第6期19卷 963-972页

作者： Maurya, Satendra Kumar Clark, Lawrence T. Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

An internet protocol (IP) router determines the next hop for a packet by finding the longest prefix match. This lookup often occurs in ternary content addressable memory (TCAM), which allows bit masking of the IP address. In this paper, an internet protocol content addressable memory (IPCAM) circuit that directly determines the longest prefix match to the stored address is described. The proposed IPCAM produces an encoded prefix match length that is limited by the prefix mask. Entries need not be sorted in order. One of the proposed IPCAM entries replaces on average 22 TCAM entries. Consequently the longest prefix matching CAM is less than 1/10 the size of the equivalent TCAM and dissipates 93.5% less dynamic power. The encoded outputs drive a priority encoder to determine the longest prefix match in the IPCAM arrays. A priority encoder circuit architecture appropriate to the unsorted IPCAM entries is also presented.

关键词： Associative memories internet protocol (IP) routing longest prefix match ternary content addressable memory (TCAM) priority encoder

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A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing

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JOURNAL OF LOW POWER ELECTRONICS 2011年第3期7卷 350-363页

作者： Maurya, Satendra Kumar Clark, Lawrence T. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA

An internet protocol (IP) router forwards packets based on their destination address by finding the longest matching prefix in internal lookup tables. In this paper, a fully static CAM that directly determines the next hop among the stored addresses is described. The proposed design achieves high lookup throughput, optimal memory utilization, integrated priority encoding, and high power efficiency. The proposed address look up architecture is 81.2% more energy efficient than a TCAM implementation while achieving 1.6x higher operating frequency. The proposed CAM uses 67.2% less energy than a previous dynamic internet protocol CAM (IPCAM) design. Simulations carried out using a bulk CMOS 65-nm foundry process show the proposed IPCAM circuits can operate above 1 GHz. With dynamic voltage scaling to V-DD = 0.6 V, the proposed design uses 0.85 fJ/bit/search at speeds adequate for 10 G Ethernet requirements. The all static design is amenable to automated circuit design flows, as demonstrated by porting to a commercial 45-nm cell library implementation, and can be pipelined. Finally, the proposed circuit architecture is shown to be scalable to IPv6.

关键词： Associative Memories Router CIDR IPv4 Internet Protocol (IP) Routing Longest Prefix Match Content Addressable Memory (CAM) Ternary CAM (TCAM) priority encoder IPv6 Scalability

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