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35th IEEE Workshop on Signal Processing Systems (IEEE SiPS)

作者： Tang, Chengcheng Han, Jie Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

ISBN: (纸本)9781665401449

The emergence of spiking neural networks (SNNs) provide a promising approach to the energy efficient design of artificial neural networks (ANNs). The rate encoded computation in SNNs utilizes the number of spikes in a time window to encode the intensity of a signal, in a similar way to the information encoding in stochastic computing. Inspired by this similarity, this paper presents a hardware design of stochastic SNNs that attains a high accuracy. A design framework is elaborated for the input, hidden and output layers. This design takes advantage of a priority encoder to convert the spikes between layers of neurons into index-based signals and uses the cumulative distribution function of the signals for spike train generation. Thus, it mitigates the problem of a relatively low information density and reduces the usage of hardware resources in SNNs. This design is implemented in field programmable gate arrays (FPGAs) and its performance is evaluated on the MNIST image recognition dataset. Hardware costs are evaluated for different sizes of hidden layers in the stochastic SNNs and the recognition accuracy is obtained using different lengths of stochastic sequences. The results show that this stochastic SNN framework achieves a higher accuracy compared to other SNN designs and a comparable accuracy as their ANN counterparts. Hence, the proposed SNN design can be an effective alternative to achieving high accuracy in hardware constrained applications.

关键词： Field programmable gate arrays (FPGAs) priority encoder stochastic computing spiking neural networks

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Design and Analysis of Memristor-based Combinational Circuits

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IETE JOURNAL OF RESEARCH 2020年第2期66卷 182-191页

作者： Singh, Anuradha NSIT TRF Dept Elect New Delhi 110075 India

This paper presents a novel memristor-based combinational circuit, namely: 4:2 priority encoders, 2:4 decoder, and BCD to EX-3 code converter. The performance of all these logic circuits is analyzed with respect to equivalent CMOS. The proposed work extends the philosophy of designing gate level circuit and then using the basic gate design to implement the combinational circuit. Memristor gates are used to implement the desired logic function. In the proposed work, memristor-based novel XOR gate is designed. This gate is then utilized to implement the encoder, decoder, and BCD to EX-3 code converter circuits. The proposed circuits have the advantage like low transistor count, high speed, and low power. The simulation is carried out in LTSPICE.

关键词： BCD-Ex 3 code converter Combinational logic Decoder Memristor priority encoder

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Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems

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IEEE EMBEDDED SYSTEMS LETTERS 2020年第4期12卷 113-116页

作者： Raj, Marshal Gopalakrishnan, Lakshminarayanan Ko, Seok-Bum Naganathan, Nagi Ramasubramanian, N. Natl Inst Technol Dept Elect & Commun Engn Tiruchirappalli 620015 Tamil Nadu India Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5A9 Canada Broadcom Ltd Allentown PA 18109 USA Natl Inst Technol Dept Comp Sci & Engn Tiruchirappalli 620015 India

Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine.

关键词： Decoder flip-flop memory cell multiplexer priority encoder quantum-dot cellular automata (QCA)

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Widening and narrowing of time interval due to single-event transients in 45nm vernier-type TDC

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IET CIRCUITS DEVICES & SYSTEMS 2017年第6期11卷 676-681页

作者： Ramaniharan, Pasupathy K. Boby, Bindu VIT Univ Sch Elect Engn Chennai CampusVandalur Kelambakkam Rd Madras Tamil Nadu India

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45nm vernier-type TDC with a resolution of 7ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

关键词： time-digital conversion radiation hardening (electronics) delay lines single-event transients SET vernier-type TDC time interval time-to-digital converter heavy-ion strikes HIS radiation environment electronic component space applications cadence spectre circuit simulator START-STOP pulse transition top-bottom voltage-controlled delay line VCDL regular staircase pattern staircase transfer characteristics D-flip-flop priority encoder guard gate technique size 45 nm

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A DNA kinetics competition strategy of hybridization chain reaction for molecular information processing circuit construction

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CHEMICAL COMMUNICATIONS 2017年第11期53卷 1789-1792页

作者： Tang, Weiyang Huang, Qichen Yang, Zhenjie Zheng, Qiwei Wang, Lihong Zhang, Junmin Chen, Liang Zhou, Xuechang Liu, Yizhen Hu, Jiming Shenzhen Univ Coll Chem & Environm Engn Shenzhen Peoples R China Shenzhen Univ Coll Informat Engn Shenzhen Peoples R China Wuhan Univ Key Lab Analyt Chem Biol & Med Minist Educ Coll Chem & Mol Sci Wuhan Peoples R China

Herein we propose a hybridization chain reaction based kinetics competition strategy able to recognize the combination/sequence of input signals. Further, a DNA priority encoder and a keypad lock were constructed. Thi... 详细信息

关键词： multi-input Information Processing priority encoder Kinetics AUTOMATIC hybridization chain reaction A-DNA keypad lock

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Multi-scroll chaotic attractors from a generalized time-delay sampled-data system

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2016年第6期44卷 1263-1276页

作者： Yeniceri, Ramazan Yalcin, Muestak E. Istanbul Tech Univ Dept Elect & Commun Engn TR-34469 Istanbul Turkey

In this paper, the first generalization for time-delay sampled-data chaotic system in order to generate multi-scroll attractor is introduced with its circuit implementation. An efficient delay-line with binary priority encoding, parallel shifting, and binary decoding is also suggested and implemented to overcome the delay line realization drawback in such systems. The proposed system enhances the complexity of chaotic behavior by means of multi-scroll feature and exemplifies the simplification of chaotic systems for better realizations. Copyright (c) 2015 John Wiley & Sons, Ltd.

关键词： chaos multi-scroll chaotic attractor delay delay line priority encoder FPGA

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Automatic Water Level Sensor and Controller System 5

Automatic Water Level Sensor and Controller System

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5th International Conference on Electronic Devices, Systems and Applications (ICEDSA)

作者： Getu, Beza Negash Attia, Hussain A. Amer Univ Ras Al Khaimah Dept Elect Elect & Commun Engn Ras Al Khaymah U Arab Emirates

ISBN: (纸本)9781509053063

In this paper, we investigate the design of a water level sensor device that is able to detect and control the level of water in a certain water tank or a similar water storage system. The system firstly senses the amount of water available in the tank by the level detector part and then adjusts the state of the water pump in accordance to the water level information. This electronic design achieves automation through sequential logic implemented using a flip flop. A seven segment display and a relay-based motor pump driving circuit are part of this integrated design. The water pump automatically turns on and starts filling the tank when the water level is empty or level ONE and turned-off and stop filling the tank when water level reaches maximum-level NINE;furthermore, the water pump will remain in its standstill state from level EIGHT down to TWO when the level is decreasing due to water consumption.

关键词： water level sensor seven segment display priority encoder water pump relay JK flip-flop motor driving circuit

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Implementation of Combinational circuits via Material Implication using Memristors

Implementation of Combinational circuits via Material Implic...

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IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)

作者： Chakraborty, Anindita Rahaman, Hafizur Indian Inst Engn Sci & Technol Sibpur India

ISBN: (纸本)9781509016235

Memristor is a new nanoelectronic device that has become very popular at recent times for its non-volatility, better alignment and excellent scalability properties. Various research works are going on designing of logic circuits, digital memory and neuromorphic systems using this nano device. Both pure and hybrid approaches are followed for the design purpose. Material implication logic brings in the motivation for exploring memristors in the area of logic design. In this work material implication logic has been applied to design complex combinational circuits like demultiplexer, encoder, priority encoder, decoder and magnitude comparator using memristors. Both serial and parallel approaches have been used for the design purpose and the parallel implementations require lesser step counts than their serial counterparts. Also the designs presented occupy lesser area than their conventional CMOS-peers.

关键词： Memristor imply demultiplexer priority encoder encoder decoder magnitude comparator

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Cdc :: 1700 :: Cyber 18 :: 76361225A Cyber18-20 Io 1983

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2016年

Cdc :: 1700 :: Cyber 18 :: 76361225A Cyber18-20 Io 1983 by published by

关键词： 76361225a address baud rate controller cyber cyber18-20 data data flow gate input input output interrupt interrupt address interrupt register interrupt system mask mask register output priority encoder signal text cyber timing generator

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Z-TCAM: An SRAM-based Architecture for TCAM

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第2期23卷 402-406页

作者： Ullah, Zahid Jaiswal, Manish K. Cheung, Ray C. C. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave like TCAM? This brief proposes a novel memory architecture, named Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM subtables, which are then processed to map on their corresponding memory blocks. Two example designs for Z-TCAM of sizes 512 x 36 and 64 x 32 have been implemented on Xilinx Virtex-7 field-programmable gate array. The design of 64x32 Z-TCAM has also been implemented using OSUcells library for 0.18 mu m technology, which confirms the physical and technical feasibility of Z-TCAM. Search latency for each design is three clock cycles. The detailed implementation results and power measurements for each design have been reported thoroughly.

关键词： Application-specific integrated circuit (ASIC) field-programmable gate array (FPGA) memory architecture priority encoder static random access memory (SRAM)-based TCAM ternary content addressable memory (TCAM)

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