检索结果-内蒙古大学图书馆

Advanced Integration-Inspired process-in-memory: A Comprehensive Review of Design, Challenges, and Future Prospects

IEEE ACCESS 2024年 12卷 160957-160972页

作者： Cheng, Jinhui Guan, Zhaoliang Fu, Jiangduo Xu, Hangyu Ke, Jinkun State Grid Smart Grid Res Inst Co Ltd State Key Lab Adv Power Transmiss Technol Beijing 102209 Peoples R China

This work provides a comprehensive overview of advanced integration-inspired memory process design, focusing on the integration methods of 2D, 2.5D, and 3D. The integration of compute and memory blocks has demonstrated encouraging outcomes in enhancing memory access latency and energy efficiency for data-centric operations. The challenges and future prospects for PIM design include addressing trade-offs in the integration process, thermal management in highly integrated 3D designs, developing design automation tools for 3D designs, and identifying practical application scenarios for PIM to maximize its benefits. The use of through-silicon vias (TSVs) technology enables the efficient design of 3D structures with improved bandwidth density, while hybrid bonding technology shows advantages in achieving higher interconnect density and data transmission bandwidth. Monolithic integration represents a distinctive solution for high-density module integration, whereby custom circuit layers are stacked vertically in a single chip. This approach represents an efficient alternative to traditional 2D integration technologies. These advances in integration technology provide a roadmap for the future of PIM design and its application in real-world scenarios. In conclusion, the continuous development and integration of different technologies in PIM design has the potential to significantly enhance performance, energy efficiency, and integration density for data-centric tasks.

关键词： Computer architecture memory management Three-dimensional displays Logic Microprocessors Bandwidth Data communication Artificial intelligence SRAM cells Energy efficiency process-in-memory heterogeneous integration near-memory computing

来源：评论

学校读者我要写书评

暂无评论

High-Performance process-in-memory Architectures Design and Security Analysis

High-Performance Process-in-Memory Architectures Design and ...

引用

作者： Wang, Ziyu University of Michigan

学位级别：Ph.D., Doctor of Philosophy

The performance of processor-centric von Neumann architectures is greatly hindered by data movement between memory and processor, especially when encountering data-intensive tasks. memory-centric process-in-memory (PIM) architectures perform computations directly within the memory modules. Hence, the performance and energy penalty associated with data access can be mitigated by minimizing data movement and leveraging high internal bandwidth. In addition to the benefits in performance and energy efficiency, PIM architectures facilitate extensive computing parallelism and scalability, while also provide enhanced security resilience against bus-snoop attacks. PIM architectures have shown their capability in many machine learning applications. Nonetheless, effectively accommodating ultra-large deep neural network (DNN) models, like Transformer, remains an ongoing challenge, and with the continued adoption of PIM architectures, security and vulnerability issues are poised to become looming threats. This dissertation focuses on high-performance PIM architecture design for data-intensive applications. To facilitate PIM architecture design and security studies, the dissertation first proposes event-driven, cycle-accurate simulators and their implementations for PIM architectures based on dynamic random-access memory (DRAM) and resistive random-access memory (RRAM), along with how these simulators can be used for architecture design. The PIM-GPT architecture is then introduced, which offers high performance, high energy efficiency and end-to-end acceleration of GPT inference. PIM-GPT leverages DRAM-based PIM solutions to perform multiply-accumulate (MAC) operations on the DRAM chips, working together with an application-specific integrated chip (ASIC) which supports data communication and other necessary arithmetic computations. At the software level, the mapping scheme is designed to maximize data locality and computation parallelism by partitioning a matrix among DRAM chan

关键词： process-in-memory Machine learning accelerator Side-channel attack Hardware security Dynamic random-access memory Resistive random-access memory

来源：评论

学校读者我要写书评

暂无评论

Pj-AxMTJ: process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction 18

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switchi...

引用

18th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Cai, Hao Jiang, Honglan Han, Menglin Wang, Zhaohao Wang, You Yang, Jun Han, Jie Liu, Leibo Zhao, Weisheng Southeast Univ Natl ASIC Syst Engn Ctr Nanjing 210096 Peoples R China Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Beihang Univ Fert Beijing Inst BDBC Beijing 100191 Peoples R China Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 1H9 Canada

ISBN: (纸本)9781728133911

In order to realize high efficient magnetization switching in magnetic tunnel junction (MTJ), several potential alternative mechanisms have been realized to replace spin transfer torque (STT) method, such as the STT-assisted precessional voltage controlled magnetic anisotropy (VCMA), and the spin orbit torque (SOT) erasing plus STT programing. In this paper, we propose a method denoted as the process-in-memory with Joint magnetization switching for Approximate computing in Magnetic Tunnel Junction (Pj-AxMTJ), by using the 1T-1M and 3T-1M bit-cell structures. The proposed method aims to implement a low-precision computational memory with dynamic approximate computing. Specifically, four nonvolatile approximate full adders (AxFAs) are proposed based on the writing operations of different types of magnetic random access memory. As no peripheral circuits but the memory bit-cells are used in the proposed design, the resultant area is significantly small. Moreover, the AxFAs can be easily reconfigured into memory units with simple wire connections. The simulation results for the proposed designs are then presented to show the precision-power-area-speed tradeoffs for addition operation. Finally, the accuracy of the AxFAs are further evaluated in an image processing application.

关键词： Approximate computing process-in-memory magnetic tunnel junction with joint switching STT-assisted VCMA SOT erasing STT programming

来源：评论

学校读者我要写书评

暂无评论

Efficient process-in-memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM 19

Efficient Process-in-Memory Architecture Design for Unsuperv...

引用

29th Great Lakes Symposium on VLSI (GLSVLSI)

作者： Chen, Fan Song, Linghao Li, Hai Helen Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

ISBN: (纸本)9781450362528

The ending of Moore's Law makes domain-specific architecture as the future of computing. The most representative is the emergence of various deep learning accelerators. Among the proposed solutions, resistive random access memory (ReRAM) based process-in-memory (PIM) architecture is anticipated as a promising candidate because ReRAM has the capability of both data storage and in-situ computation. However, we found that existing solutions are unable to efficiently support the computational needs required by the training of unsupervised generative adversarial networks (GANs), due to the lack of the following two features: 1) Computation efficiency: GAN utilizes a new operator, called transposed convolution. It inserts massive zeros in its input before a convolution operation, resulting in significant resource under-utilization;2) Data traffic: The data intensive training process of GANs often incurs structural heavy data traffic as well as frequent massive data swaps. Our research follows the PIM strategy by leveraging the energy-efficiency of ReRAM arrays for vector-matrix multiplication to enhance the performance and energy efficiency. Specifically, we propose a novel computation deformation technique that can skip zero-insertions in transposed convolution for computation efficiency improvement. Moreover, we explore an efficient pipelined training procedure to reduce on-chip memory access. The implementation of related circuits and architecture is also discussed. At the end, we present our perspective on the future trend and opportunities of deep learning accelerators.

关键词： GAN process-in-memory ReRAM unsupervised learning

来源：评论

学校读者我要写书评

暂无评论

process-in-memory Using a Magnetic-Tunnel-Junction Synapse and a Neuron Based on a Carbon Nanotube Field-Effect Transistor

引用

IEEE MAGNETICS LETTERS 2019年 10卷 1页

作者： Amirany, Abdolah Moaiyeri, Mohammad Hossein Jafari, Kian Shahid Beheshti Univ Dept Elect Engn Tehran *** Iran

Bio-inspired computing attempts to emulate the computations performed by biological neural networks, like those in the human brain, to benefit from efficiencies in flexibility, parallel processing, and, most importantly, learning. We simulate a fully nonvolatile spin-based synapse utilizing a magnetic tunnel junction (MTJ) and a neuron based on a carbon nanotube field-effect transistor (CNTFET). The modeled synapse benefits from the features of MTJs like nonvolatility, high endurance, and reconfigurability. The features of CNTFETs are utilized to streamline the design. The functionality and characteristics of the synapse in the inevitable presence of process variations are validated using Monte Carlo simulations. An associative memory, designed and simulated using the spin-based synapse, performs very similar to its ideal software-based counterpart, with about 8% difference in successful recall rate.

关键词： Spin electronics magnetic tunnel junction carbon nanotube field-effect transistor neural network associative memory process-in-memory

来源：评论

学校读者我要写书评

暂无评论

AligneR: A process-in-memory Architecture for Short Read Alignment in ReRAMs

IEEE COMPUTER ARCHITECTURE LETTERS

引用

IEEE COMPUTER ARCHITECTURE LETTERS 2018年第2期17卷 235-238页

作者： Zokaee, Farzaneh Zarandi, Hamid R. Jiang, Lei Indiana Univ Bloomington IN 47405 USA Amirkabir Univ Technol Tehran 158754413 Iran

Genomics is the key to enable the personal customization of medical care. How to fast and energy-efficiently analyze the huge amounts of genomic sequence data generated by next generation sequencing technologies has become one of the most significant challenges facing genomics today. Existing hardware platforms achieve low genome sequencing throughput with significant hardware and power overhead. In this paper, we propose AligneR, a ReRAM-based process-in-memory architecture, to accelerate the bottleneck of genome sequencing, i.e., short read alignment. Compared to state-of-the-art accelerators, AligneR improves the short read alignment throughput per Watt per mm(2) by 13x.

关键词： Genome sequencing short read alignment FM-index process-in-memory ReRAM

来源：评论

学校读者我要写书评

暂无评论

3DICT: A Reliable and QoS Capable Mobile process-in-memory Architecture for Lookup-based CNNs in 3D XPoint ReRAMs 18

3DICT: A Reliable and QoS Capable Mobile Process-In-Memory A...

引用

37th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Lou, Qian Wen, Wujie Jiang, Lei Indiana Univ Bloomington IN 47401 USA Florida State Univ Tallahassee FL 32306 USA

ISBN: (纸本)9781450359504

It is extremely challenging to deploy computing-intensive convolutional neural networks (CNNs) with rich parameters in mobile devices because of their limited computing resources and low power budgets. Although prior works build fast and energy-efficient CNN accelerators by greatly sacrificing test accuracy, mobile devices have to guarantee high CNN test accuracy for critical applications, e.g., unlocking phones by face recognitions. In this paper, we propose a 3D XPoint ReRAM-based process-in-memory architecture, 3DICT, to provide various test accuracies to applications with different priorities by lookup-based CNN tests that dynamically exploit the trade-off between test accuracy and latency. Compared to the state-of-the-art accelerators, on average, 3DICT improves the CNN test performance per Watt by 13% 61x and guarantees 9 -year endurance under various CNN test accuracy requirements.

关键词： 3D vertical ReRAM Lookup -based CNN process-in-memory

来源：评论

学校读者我要写书评

暂无评论

Bidirectional Database Storage and SQL Query Exploiting RRAM-Based process-in-memory Structure

引用

ACM TRANSACTIONS ON STORAGE 2018年第1期14卷 8-8页

作者： Sun, Yuliang Wang, Yu Yang, Huazhong Tsinghua Univ TNList Elect Engn Dept Rohm Bldg Beijing Peoples R China

With the coming of the "Big Data" era, a high-energy-efficiency database is demanded for the Internet of things (IoT) application scenarios. The emerging Resistive Random Access memory (RRAM) has been considered as an energy-efficient replacement of DRAM for next-generation main memory. In this article, we propose an RRAM-based SQL query unit with process-in-memory (PIM) characteristics. A bidirectional storage structure for a database in RRAM crossbar array is proposed that avoids redundant data transfer to cache and reduces cache miss rate compared with the storage method in DRAM for an in-memory database. The proposed RRAM-based SQL query unit can support a representative subset of SQL queries in memory and thus can further reduce the data transfer cost. The corresponding query optimization method is proposed to fully utilize the PIM characteristics. Simulation results show that the energy efficiency of the proposed RRAM-based SQL query unit is increased by 4 to 6 orders of magnitudes compared with the traditional architecture.

关键词： NVM-based databases process-in-memory RRAM

来源：评论

学校读者我要写书评

暂无评论

HaLo-FL: Hardware-Aware Low-Precision Federated Learning

HaLo-FL: Hardware-Aware Low-Precision Federated Learning

引用

27th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Venkatesha, Yeshwanth Bhattacharjee, Abhiroop Moitra, Abhishek Panda, Priyadarshini Yale Univ Dept Elect Engn New Haven CT 06520 USA

ISBN: (纸本)9798350348606;9783981926385

Applications of federated learning involve devices with extremely limited computational resources and often with considerable heterogeneity in terms of energy efficiency, latency tolerance, and hardware area. Although low-precision training methods have demonstrated effectiveness in accommodating the device constraints in a centralized setting, their applicability in distributed learning scenarios featuring heterogeneous client capabilities has not been well explored. In this work, we design a hardware-aware low-precision federated training framework (HaLo-FL) tailored to heterogeneous resource-constrained devices. In particular, we optimize the precision for weights, activations, and errors for each client's hardware constraint using a precision selector (named HaLo-PS). To validate our approach, we propose HaLoSim, a hardware evaluation platform that enables precision reconfigurability and evaluates hardware metrics like energy, latency, and area utilization on a crossbar-based In-memory Computing (IMC) platform.

关键词： In-memory Computing process-in-memory Federated Learning Quantization

来源：评论

学校读者我要写书评

暂无评论

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC processor using IMC 37

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel M...

引用

37th International Conference on VLSI Design (VLSID) / 23rd International Conference on Embedded Systems (ES)

作者： Gajawada, Saketh Gupta, Aryan Prasad, Kailash Mekie, Joycee IIIT Bangalore Bangalore Karnataka India IIT Gandhinagar Gandhinagar India

ISBN: (纸本)9798350384406

In-memory computing (IMC) has emerged as a promising solution to address the energy and performance bottlenecks of traditional von Neumann architectures. This paper presents FP-BMAC, a novel bit-parallel in-memory computing architecture that efficiently handles floating-point multiply-and-accumulate (MAC) operations with reconfigurable FP precision. The architecture employs a novel approach to compute mantissa bits using an approximate right-shift multiplication method, which ensures alignment of output mantissa length with the input and enhances storage efficiency. The architecture effectively reduces computation delays and improves overall performance by incorporating BL Separator and BL Boosting circuits. The bit-parallel IMC macro achieves remarkable energy efficiency improvements, achieving a normalized throughput of 12.19 GFLOPS/Kb for FP Multiplication and 16.94 TFLOPS/W for MAC Operation at 1.15 GHz in CMOS 28nm technology.

关键词： In-memory Computing process-in-memory Approximate Computing Floating Point

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：