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PIM-IoT: Enabling hierarchical, heterogeneous, and agile processing-in-memory in IoT systems

FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2025年 169卷

作者： Zhong, Kan Li, Qiao Ren, Ao Tan, Yujuan Chen, Xianzhang Long, Linbo Liu, Duo Chongqing Univ Sch Bigdata & Software Engn 174 Shazhengjie Chongqing 400044 Peoples R China Univ Elect Sci & Technol China Sch Comp Sci & Engn 2006 Xiyuan Ave Chengdu 611731 Peoples R China Chongqing Univ Coll Comp Sci 174 Shazhengjie Chongqing 400044 Peoples R China Chongqing Univ Posts & Telecommun Sch Comp Sci & Technol 2 Chongwen Rd Chongqing 400065 Peoples R China

The Internet of Things (IoT) is an emerging concept that senses the physical world by connecting various "things"and objects to the Internet. Conventional cloud-based IoT systems are unlikely to keep up with the diverse needs of IoT applications and have some issues, such as privacy and latency. Edge computing based IoT systems solve these issues by placing data processing and inference tasks near the data source. However, due to the increasing complexity of IoT applications, performing data processing and inference tasks in edge computing based IoT systems can lead to high energy consumption and latency. processing-in-memory (PIM) is a promising solution to reduce the energy consumption of data processing and inference tasks by closely integrating computational logics with memory device. Therefore, in this paper, we propose PIM-IoT, a PIM architectures enabled IoT system to reduce the energy consumption. To accommodate various data processing tasks, we architect PIM-IoT as a hierarchical system that consists of 3 tiers: sensing tier, gateway tier, and edge computing tier. We first analyze the dataflow of typical IoT applications and map tasks to different tiers. To handle the data processing and inference tasks effectively in each tier, we then propose hierarchical, heterogeneous, and collaborative PIM architectures for each tier. Finally, we show how multi-tier can be co-optimized under latency and power constraints. To our knowledge, this is the first work to explore novel PIM architectures in IoT systems. Detailed analysis and experimental results show that PIM-IoT can achieve 5.6x performance improvement and 6x energy consumption reduction for IoT applications.

关键词： processing in memory Internet of Things 3-tier IoT system IoT application modeling

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processing in memory Assisted MEC 3C Resource Allocation for Computation Offloading 20th

Processing in Memory Assisted MEC 3C Resource Allocation for...

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20th International Conference on Algorithms and Architectures for Parallel processing (ICA3PP)

作者： Yang, Yang Chang, Xiaolin Jia, Ziye Han, Zhu Han, Zhen Beijing Jiaotong Univ Beijing Key Lab Secur & Privacy Intelligent Trans Beijing Peoples R China Xidian Univ Informat Sci Inst State Key Lab ISN Xian Peoples R China Univ Houston Dept Elect & Comp Engn Houston TX USA

ISBN: (纸本)9783030602451;9783030602444

The improvement of Internet of Things (IoT) applications has led to a substantial increase in the number of multiple resources of computation, communication, and caching (3C). The fifth generation (5G) and multi-access edge computing (MEC) are promising to enhance the computation offloading of IoT applications with high performance and reliability. According to resource-consuming preferences, IoT applications can be divided into computation-hungry applications and memory-hungry applications. To deal with the computation-hungry applications, Graphics processing Units (GPUs) are increasingly used to process simple computation tasks. Meanwhile, the running of memory-hungry applications is accompanied by massive data transfers between processing core and memory. These transfers can result in significant energy and performance costs. processing in memory (PIM) is a computing paradigm that avoids most data movement costs by performing a part of the computations directly in the memory. In this paper, we focus on offloading computation tasks in MEC that require 3C resources with high efficiency and low energy consumption considering latency and resilience constraints in a PIM-assisted multi-core (PAMC) architecture of physical machines (PMs). We formulate an optimization problem to minimize the total weighted resource costs and energy consumption. We also present an algorithm based on the column generation to solve the problem. Simulation results demonstrate that the proposed PAMC architecture can achieve good results in terms of energy consumption and resources utilization in comparison with the traditional PMs' architecture with the same resources.

关键词： Column generation Computation offloading GPU Multi-access edge computing processing in memory

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A Case For Asymmetric processing in memory

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2019年第1期18卷 22-25页

作者： Akin, Berkin Alameldeen, Alaa R. Intel Labs Hillsboro OR 97124 USA

By sidestepping the limitations at the memory interface, processing-in-memory (PIM) unlocks internally available memory bandwidth to the compute units on the memory side. This abundant bandwidth is conventionally utilized by highly-parallel throughput-oriented many-core style PIM architectures via offloading bandwidth-bound parallel tasks. However, it can be difficult to fully isolate these PIM-suitable tasks, and an offloaded program may include compute-bound sequential phases. These PIM-averse phases constitute a critical performance bottleneck for conventional many-core style PIM architectures. In this paper, we propose an analytical model for PIM execution that considers a program's bandwidth demand as well as its parallelism. Based on the proposed model, we make a case for an asymmetric PIM architecture that can mitigate the performance bottlenecks for PIM-averse phases while keeping the performance upside for PIM-suitable phases.

关键词： processing in memory analytical performance model asymmetric multicore parallel processing

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A Mini Tutorial of processing in memory: From Principles, Devices to Prototypes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第7期69卷 3044-3050页

作者： Pan, Biao Wang, Guangyao Zhang, He Kang, Wang Zhao, Weisheng Beihang Univ Sch Integrated Circuit Sci & Engn Fert Beijing Inst Beijing 100191 Peoples R China

Data movement overheads caused by the recent explosion in big data applications have made traditional von Neumann architecture fails to tackle big data workloads. processing in memory (PIM), where computational tasks are performed within the memory, has drawn increasing attention. To present meaningful insights to readers, we divide current PIM paradigm into charge-based and resistance-based categories according to different memory devices. This mini tutorial aims to provide a concise overview of the implementation of PIM schemes, highlighting important macro prototypes in artificial intelligence applications that have been released in the past five years.

关键词： Random access memory Virtual machine monitors Resistance Transistors Task analysis Nonvolatile memory Energy efficiency processing in memory SRAM DRAM RRAM MRAM

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An Ultra-efficient Look-up Table based Programmable processing in memory Architecture for Data Encryption 39

An Ultra-efficient Look-up Table based Programmable Processi...

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39th IEEE International Conference on Computer Design ICCD)

作者： Sutradhar, Purab Ranjan Basu, Kanad Dinakarrao, Sai Manoj Pudukotai Ganguly, Amlan Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ Texas Dallas Dept Elect & Comp Engn Dallas TX USA George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781665432191

processing in memory (PIM), a non-von Neumann computing paradigm, has emerged as a faster and more efficient alternative to the traditional computing devices for data-centric applications such as Data Encryption. In this work, we present a novel PIM architecture implemented using programmable Look-up Tables (LUT) inside a DRAM chip to facilitate massively parallel and ultra-efficient data encryption with the Advanced Encryption Standard (AES) algorithm. Its LUT-based architecture replaces logic-based computations with LUT 'look-ups' to minimize power consumption and operational latency. The proposed PIM architecture is organized as clusters of homogeneous, interconnected LUTs that can be dynamically programmed to execute operations required for performing AES encryption. Our simulations show that the proposed PIM architecture can offer up to 14.6x and 1.8 x higher performance compared to CUDA-based implementation of AES Encryption on a high-end commodity GPU and a state-of-the-art GPU Computing Processor, respectively. At the same time, it also achieves 217 x and 31.2 x higher energy efficiency, respectively, than the aforementioned devices while performing AES Encryption.

关键词： processing in memory DRAM Data Encryption AES

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Crossbar based processing in memory Accelerator Architecture for Graph Convolutional Networks 40

Crossbar based Processing in Memory Accelerator Architecture...

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40th IEEE/ACM International Conference on Computer Aided Design (ICCAD)

作者： Challapalle, Nagadastagiri Swaminathan, Karthik Chandramoorthy, Nandhini Narayanan, Vijaykrishnan Penn State Univ University Pk PA 16802 USA IBM TJ Watson Res Ctr Ossining NY USA

ISBN: (纸本)9781665445078

Graph data structures are central to many applications such as social networks, citation networks, molecular interactions, and navigation systems. Graph Convolutional Networks (GCNs) are used to process and learn insights from the graph data for tasks such as link prediction, node classification, and learning node embeddings. The compute and memory access characteristics of GCNs differ, both from conventional graph analytics algorithms and from convolutional neural networks, rendering the existing accelerators for graph analytics as well as deep learning, inefficient. In this work, we propose PIM-GCN, a crossbar-based processing-in-memory (PIM) accelerator architecture for GCNs. PIM-GCN incorporates a node-stationary dataflow with support for both Compressed Sparse Row (CSR) and Compressed Sparse Column (CSC) graph data representations. We propose techniques for graph traversal in the compressed sparse domain, feature aggregation, and feature transformation operations in GCNs mapped to in-situ analog compute functions of crossbar memory, and present the trade-offs in performance, energy, and scalability aspects of the PIM-GCN architecture for CSR, and CSC graph data representations. PIM-GCN shows an average speedup of over 3-16x and an average energy reduction of 4-12x compared to the existing accelerator architectures.

关键词： processing in memory graph convolution network aggregation transformation node features

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Evaluating HPC Kernels for processing in memory

Evaluating HPC Kernels for Processing in Memory

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International Symposium on memory Systems (MEMSYS)

作者： Asifuzzaman, Kazi Monil, Mohammad Alaul Haque Liu, Frank Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450398008

memory subsystems contribute significantly to the performance and energy efficiency of high-performance computing (HPC) applications. Traditional memory technologies with conventional organization (e.g., DRAM) are struggling to keep up with the increasing memory requirements of modern applications. Techniques such as multilayer cache hierarchy and out-of-order execution are still falling short of mitigating the penalty incurred by memory accesses. processing-in-memory (PIM), which involves moving memory-intensive kernels to memory for execution instead of bringing the data to the processing unit, is emerging as a promising technique. PIM has recently received traction among computer architecture researchers, and the increasing research activity surrounding this technique indicates its potential to alleviate main memory performance bottlenecks. In this paper, we characterize and identify memory-intensive HPC kernels, perform a first-order evaluation of the PIM technique for selected HPC kernels, quantify performance deviation, and analyze the key factors that affect PIM efficiency.

关键词： processing in memory High-Performance Computing

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Emulation of processing in memory Architecture for Application Development 13

Emulation of Processing in Memory Architecture for Applicati...

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International SoC Design Conference (ISOCC)

作者： Kwon, Jin-San Hwang, Tae-Ho Kim, Dong-Sun Korea Elect Technol Inst Seongnam South Korea

ISBN: (纸本)9781509032198

Since the new technologies like big data and cloud computing require tremendous amount of transactions between processors and memory, researches on a new memory system called processing in memory (PIM) architecture has been suggested as a solution for those memory intensive applications. To make software utilize the new architecture, a development environment with tool chain and debug infrastructures supplementing extended instruction sets and target emulation is needed. This paper introduces a way to emulate a target platform having PIM architecture memory device. The emulated platform may use the PIM device as a system memory or simple memory mapped bus device. The actual PIM architecture is implemented in both cycle-based memory simulator and FPGA based hardware platform. The emulator has a bridge for these implementations so the emulated target platform may be freely used with early stage application development for the PIM architecture.

关键词： processing in memory QEMU memory simulator

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FlutPIM: A Look-up Table-based processing in memory Architecture with Floating-point Computation Support for Deep Learning Applications 23

FlutPIM: A Look-up Table-based Processing in Memory Architec...

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Sutradhar, Purab Ranjan Bavikadi, Sathwika Indovina, Mark Dinakarrao, Sai Manoj Pudukotai Ganguly, Amlan Rochester Inst Technol Rochester Dept Comp Engn New York NY 14623 USA George Mason Univ Dept Elect & Comp Engn Fairfax VA USA

ISBN: (纸本)9798400701252

processing-in-memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learning and AI. However, it is a challenge to facilitate the computational sophistication of a standard processor (i.e. CPU or GPU) within the limited scope of a memory chip without contributing significant circuit overheads. To address the challenge, we propose a programmable LUT-based area-efficient PIM architecture capable of performing various low-precision floating point (FP) computations using a novel LUT-oriented operand-decomposition technique. We incorporate such compact computational units within the memory banks in a large count to achieve impressive parallel processing capabilities, up to 4x higher than state-of-the-art FP-capable PIM. Additionally, we adopt a highly-optimized low-precision FP format that maximizes computational performance at a minimal compromise of computational precision, especially for Deep Learning Applications. The overall result is a 17% higher throughput and an impressive 8-20x higher compute Bandwidth/bank compared to the state-of-the-art of in-memory acceleration.

关键词： processing in memory Floating Point DRAM Deep Learning

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Implementation and Evaluation of Deep Neural Networks in Commercially Available processing in memory Hardware 35

Implementation and Evaluation of Deep Neural Networks in Com...

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35th IEEE International System-on-Chip Conference (SOCC)

作者： Das, Prangon Sutradhar, Purab Ranjan Indovina, Mark Dinakarrao, Sai Manoj Pudukotai Ganguly, Amlan Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA George Mason Univ Dept Elect & Comp Engn Fairfax VA USA Rochester Inst Technol Dept Elect & Microelect Engn Rochester NY USA

ISBN: (数字)9781665459853

ISBN: (纸本)9781665459853

Deep Neural Networks (DNNs) are often associated with a large number of data-parallel computations. Therefore, data-centric computing paradigms, such as processing in memory (PIM), are being widely explored for DNN acceleration applications. A recent PIM architecture, developed and commercialized by the UPMEM company, has demonstrated impressive performance boost over traditional CPU-based systems for a wide range of data-parallel applications. However, the application domain of DNN acceleration is yet to be explored on this PIM platform. In this work, we present successful implementations of DNNs on the UPMEM PIM system. We explore multiple operation mapping schemes with different optimization goals and accelerate two CNN algorithms using these schemes. Based on the data achieved from the physical implementation of the DNNs on the UPMEM system, we compare the performance of our DNN implementation with several other recently proposed PIM architecture.

关键词： Deep Neural Network processing in memory Real-system Characterization

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