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A survey of spintronic architectures for processing-in-memory and neural networks

JOURNAL OF SYSTEMS ARCHITECTURE 2019年 97卷 349-372页

作者： Umesh, Sumanth Mittal, Sparsh IIT Jodhpur Jodhpur Rajasthan India IIT Hyderabad C-113-A Sangareddy Hyderabad 502285 Telangana India

The rising overheads of data-movement and limitations of general-purpose processing architectures have led to a huge surge in the interest in "processing-in-memory" (PIM) approach and "neural networks" (NN) architectures. Spintronic memories facilitate efficient implementation of PIM approach and NN accelerators, and offer several advantages over conventional memories. In this paper, we present a survey of spintronic-architectures for PIM and NNs. We organize the works based on main attributes to underscore their similarities and differences. This paper will be useful for researchers in the area of artificial intelligence, hardware architecture, chip design and memory system.

关键词： Review Spin transfer torque RAM Spin orbit torque Domain wall memory processing-in-memory Machine learning Neural networks

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An 8-T processing-in-memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第11期70卷 4249-4259页

作者： Chen, Leyi Shi, Cong He, Junxian Yu, Jianyi Wang, Haibing Lu, Jing Liu, Liyuan Wu, Nanjian Tian, Min Chongqing Univ Sch Microelect & Commun Engn Chongqing 400044 Peoples R China Chinese Acad Sci Inst Semicond Beijing 100083 Peoples R China

Vision chip is a high-speed image processing device, featuring a massively-parallel pixel-level processing element (PE) array to boost pixel processing speed. However, the collocated processing unit and fine-grained data memory unit inside each PE impose a huge requirement on memory access bandwidth as well as big area and energy consumption. To overcome this bottleneck, this paper proposes a full custom 8T SRAM-based processing-in-memory (PIM) architecture together with a multiplexer-based arithmetic-logic unit (mux-based ALU) to realize pixel-parallel array processor for energy-efficient vision chips. The proposed PIM architecture is constructed by embroidering each dual-port 8T SRAM cell with mux-based ALU, so as to form a PIM PE array. Each PIM PE holds a 130-bit 8T SRAM cell block embedding in-memory logic functions, of which 128-bit 8T SRAM cells serve as the PE memory, and 2-bit 8T SRAM cells act as a buffer register in the PE. A full custom physical layout of a 128 x 128 prototyping PIM PE array is designed and evaluated using a 65 nm CMOS technology. The simulation results demonstrate that our proposed PIM PE architecture could operate under a 200 MHz clock frequency with a 1.0 V power supply, and reach a high energy efficiency of 512 GOPS/W and a high area efficiency of 29 GOPS/mm(2).

关键词： Vision chip processing-in-memory processing element pixel-parallel

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CAIRO: A Compiler-Assisted Technique for Enabling Instruction-Level Offloading of processing-in-memory

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2017年第4期14卷 1–25页

作者： Hadidi, Ramyad Nai, Lifeng Kim, Hyojong Kim, Hyesoon Georgia Inst Technol Atlanta GA 30332 USA

Three-dimensional (3D)-stacking technology and the memory-wall problem have popularized processing-in-memory (PIM) concepts again, which offers the benefits of bandwidth and energy savings by offloading computations to functional units inside the memory. Several memory vendors have also started to integrate computation logics into the memory, such as Hybrid memory Cube (HMC), the latest version of which supports up to 18 in-memory atomic instructions. Although industry prototypes have motivated studies for investigating efficient methods and architectures for PIM, researchers have not proposed a systematic way for identifying the benefits of instruction-level PIM offloading. As a result, compiler support for recognizing offloading candidates and utilizing instruction-level PIM offloading is unavailable. In this article, we analyze the advantages of instruction-level PIM offloading in the context of HMC-atomic instructions for graph-computing applications and propose CAIRO, a compiler-assisted technique and decision model for enabling instruction-level offloading of PIM without any burden on programmers. To develop CAIRO, we analyzed how instruction offloading enables performance gain in both CPU and GPU workloads. Our studies show that performance gain from bandwidth savings, the ratio of number of cache misses to total cache accesses, and the overhead of host atomic instructions are the key factors in selecting an offloading candidate. Based on our analytical models, we characterize the properties of beneficial and nonbeneficial candidates for offloading. We evaluate CAIRO with 27 multithreaded CPU and 36 GPU benchmarks. In our evaluation, CAIRO not only doubles the speedup for a set of PIM-beneficial workloads by exploiting HMC-atomic instructions but also prevents slowdown caused by incorrect offloading decisions for other workloads.

关键词： processing-in-memory instruction-level offloading compiler technique profiling Hybrid memory Cube (HMC) 3D stacking emerging technologies

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A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous processing-in-memory Architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 5546-5559页

作者： Jung, Sangwoo Lee, Jaehyun Park, Dahoon Lee, Youngjoo Yoon, Jong-Hyeok Kung, Jaeha Daegu Gyeongbuk Inst Sci & Technol DGIST Dept Elect Engn & Comp Sci Daegu 42988 South Korea Korea Univ Sch Elect Engn Seoul 02841 South Korea Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37655 South Korea

In this article, we present an energy-scalable CNN model that can adapt to different hardware resource constraints. Specifically, we propose a dual-precision network, named DualNet, that leverages two independent bit-precision paths (INT4 and ternary-binary). DualNet achieves both high accuracy and low complexity by balancing the ratio between two paths. We also present an evolutionary algorithm that allows the automatic search of the optimal ratios. In addition to the novel CNN architecture design, we develop a heterogeneous processing-in-memory (PIM) hardware that integrates SRAM-and eDRAM-based PIMs to efficiently compute two precision paths in parallel. To verify the energy efficiency of DualNet computed on the heterogeneous PIM, we prototyped a test chip in 28nm CMOS technology. To maximize the hardware efficiency, we utilize an improved data mapping scheme achieving the most effective deployment of DualNets on multiple PIM arrays. With the proposed SW-HW co-optimization, we can obtain the most energy-efficient DualNet model operating on the actual PIM hardware. Compared to the other quantized networks with a single bit-precision, DualNet reduces the energy consumption, memory footprint, and latency by 29.0%, 49.5%, 47.3% on average, respectively, for CIFAR-10/100 and ImageNet datasets.

关键词： Hardware Quantization (signal) Convolution Computational modeling Convolutional neural networks Random access memory memory management deep learning mixed-precision quantization processing-in-memory SW-HW co-optimization

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A Technologically Agnostic Framework for Cyber-Physical and IoT processing-in-memory-based Systems Simulation

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MICROPROCESSORS AND MICROSYSTEMS 2019年第Sep.期69卷 101-111页

作者： Santos, Paulo Cesar de Lima, Joao Paulo C. de Moura, Rafael F. Ahmed, Hameeza Alves, Marco A. Z. Beck, Antonio C. S. Carro, Luigi Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil NED Dept Comp & Informat Engn Karachi Pakistan UFPR Inst Informat Curitiba Parana Brazil

Smart devices based on Internet of Things (IoT) and Cyber-Physical System (CPS) are emerging as an important and complex set of applications in the modern world. These systems can generate a massive amounts of data, due to the enormous quantity of sensors being used in modern applications, which can either stress the communication mechanisms or need extra resources to treat data locally. In the era of efficient smart devices, the idea of transmitting huge amounts of data is prohibitive. Furthermore, implementing traditional architectures imposes limits on achieving the required efficiency. Within the area, power, and energy constraints, processing-in-memory(PIM) has emerged as a solution for efficiently processing big data. By using PIM, the generated data can be processed locally, with reduced power and energy costs, allowing an efficient solution for CPS and IoT data management problem. However, two main tools are fundamental on this scenario: a simulator that allows architectural performance and behavior analysis is essential within a project life-cycle, and a compiler able to automatically generate code for the targeted architecture with obvious improvements of productivity. Also, with the emergence of new technologies, the ability to simulate PIM coupled to the latest memory technologies is also important. This work presents a framework able to simulate and automatically generate code for IoT PIM-based systems. Also, supported by the presented framework, this work proposes an architecture that shows an efficient loT PIM system able to compute a real image recognition application. The proposed architecture is able to process 6 x more frames per second than the baseline, while improving the energy efficiency by 30 x. (C) 2019 Elsevier B.V. All rights reserved.

关键词： IoT CPS processing-in-memory Simulation Compiler

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PyGim : An Efficient Graph Neural Network Library for Real processing-in-memory Architectures

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PROCEEDINGS OF THE ACM ON MEASUREMENT AND ANALYSIS OF COMPUTING SYSTEMS 2024年第3期8卷 1-36页

作者： Giannoula, Christina Yang, Peiming Fernandez, Ivan Yang, Jiacheng Durvasula, Sankeerth Li, Yu xin Sadrosadati, Mohammad Luna, Juan gomez Mutlu, Onur Pekhimenko, Gennady Univ Toronto Toronto ON Canada Swiss Fed Inst Technol Zurich Switzerland Vector Inst Toronto ON Canada CentML Toronto ON Canada Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain NVIDIA Zurich Switzerland

Graph Neural Networks (GNNs) are emerging models to analyze graph-structure data. GNN execution involves both compute-intensive and memory-intensive kernels. The latter kernels dominate execution time, because they are significantly bottlenecked by data movement between memory and processors. processing-in-memory (PIM) systems can alleviate this data movement bottleneck by placing simple processors near or inside to memory arrays. This work investigates the potential of PIM systems to alleviate the data movement bottleneck in GNNs, and introduces PyGim, an efficient and easy-to-use GNN library for real PIM systems. We propose intelligent parallelization techniques for memory-intensive kernels of GNNs tailored for real PIM systems, and develop an easy-to-use Python API for them. PyGim employs a cooperative GNN execution, in which the compute- and memory-intensive kernels are executed in processor-centric and memory-centric computing systems, respectively, to fully exploit the hardware capabilities. PyGim integrates a lightweight autotuner to tune the parallelization strategy of the memory-intensive kernel of GNNs and enable high programming ease. We extensively evaluate PyGim on a real-world PIM system that has 16 PIM DIMMs with 1992 PIM cores connected to a Host CPU. In GNN inference, we demonstrate that it outperforms prior state-of-the-art PIM works by on average 4.38x (up to 7.20x), and state-of-the-art PyTorch running on Host by on average 3.04x (up to 3.44x). PyGim improves energy efficiency by 2.86x (up to 3.68x) and 1.55x (up to 1.75x) over prior PIM and PyTorch Host schemes, respectively. In memory-intensive kernel of GNNs, PyGim provides 11.6x higher resource utilization in PIM system than that of PyTorch library (optimized CUDA implementation) in GPU systems. Our work provides useful recommendations for software, system and hardware designers. PyGim is publicly and freely available at https://***/CMU-SAFARI/PyGim facilitate the widespread use of PIM

关键词： machine learning graph neural networks sparse matrix-matrix multi- plication library multicore processing-in-memory near-data processing memory systems data movement bottleneck DRAM benchmarking real-system characterization workload characterization

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GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

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BMC GENOMICS 2018年第2期19卷 23-40页

作者： Kim, Jeremie S. Cali, Damla Senol Xin, Hongyi Lee, Donghyuk Ghose, Saugata Alser, Mohammed Hassan, Hasan Ergin, Oguz Alkan, Can Mutlu, Onur Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA NVIDIA Res Austin TX USA Bilkent Univ Dept Comp Engn Bilkent Ankara Turkey TOBB Univ Econ & Technol Dept Comp Engn Ankara Turkey Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

Background: Seed location filtering is critical in DNA read mapping, a process where billions of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to identify genomic variants of the donor. State-of-the-art read mappers 1) quickly generate possible mapping locations for seeds (i.e., smaller segments) within each read, 2) extract reference sequences at each of the mapping locations, and 3) check similarity between each read and its associated reference sequences with a computationally-expensive algorithm (i.e., sequence alignment) to determine the origin of the read. A seed location filter comes into play before alignment, discarding seed locations that alignment would deem a poor match. The ideal seed location filter would discard all poor match locations prior to alignment such that there is no wasted computation on unnecessary alignments. Results: We propose a novel seed location filtering algorithm, GRIM-Filter, optimized to exploit 3D-stacked memory systems that integrate computation within a logic layer stacked under memory layers, to perform processing-in-memory (PIM). GRIM-Filter quickly filters seed locations by 1) introducing a new representation of coarse-grained segments of the reference genome, and 2) using massively-parallel in-memory operations to identify read presence within each coarse-grained segment. Our evaluations show that for a sequence alignment error tolerance of 0.05, GRIM-Filter 1) reduces the false negative rate of filtering by 5.59x-6.41x, and 2) provides an end-to-end read mapper speedup of 1.81x-3.65x, compared to a state-of-the-art read mapper employing the best previous seed location filtering algorithm. Conclusion: GRIM-Filter exploits 3D-stacked memory, which enables the efficient use of processing-in-memory, to overcome the memory bandwidth bottleneck in seed location filtering. We show that GRIM-Filter significantly improves the performance of a state-of-the-art read mapper. GRIM-Filter is a universal

关键词： High throughput sequencing Genome sequencing Seed location filtering 3D-stacked DRAM processing-in-memory Emerging memory technologies

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Voltage-Controlled Magnetic Tunnel Junctions for processing-in-memory Implementation

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2018年第3期39卷 440-443页

作者： Wang, Lezhi Kang, Wang Ebrahimi, Farbod Li, Xiang Huang, Yangqi Zhao, Chao Wang, Kang L. Zhao, Weisheng Beihang Univ Fert Beijing Res Inst Big Data & Brain Comp Ctr Beijing 100191 Peoples R China Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

The processing-in-memory (PIM) paradigm has been considered as a promising alternative to break the bottlenecks of conventional von-Neumann architecture by realizing the unity of data storage and processing in the same die. On the road toward implementing such an architecture, finding a novel memory that can support both dense data storage and efficient logic processing is the critical step. In this letter, we report a voltage-controlled magnetic tunnel junction (MTJ), which is a potential candidate for PIM implementation. Stateful Boolean logic functions can be realized with a single device through the memory-like write/ read operations. The device was fabricated and characterized at room temperature. Afterwards, typical Boolean logic operations, e.g., "OR", "AND", and "NXOR", were experimentally demonstrated with the fabricated MTJ device. The proposed approach opens up a new way for PIM implementation in spintronic memories.

关键词： Magnetic tunnel junction processing-in-memory voltage-controlled magnetic anisotropy

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MultPIM: Fast Stateful Multiplication for processing-in-memory

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第3期69卷 1647-1651页

作者： Leitersdorf, Orian Ronen, Ronny Kvatinsky, Shahar Technion Israel Inst Technol Erna Viterbi Fac Elect & Comp Engn IL-3200003 Haifa Israel

processing-in-memory (PIM) seeks to eliminate computation/memory data transfer using devices that support both storage and logic. Stateful logic techniques such as IMPLY, MAGIC and FELIX can perform logic gates within memristive crossbar arrays with massive parallelism. Multiplication via stateful logic is an active field of research due to the wide implications. Recently, RIME has become the state-of-the-art algorithm for stateful single-row multiplication by using memristive partitions, reducing the latency of the previous state-of-the-art by 5.1x. In this brief, we begin by proposing novel partition-based computation techniques for broadcasting and shifting data. Then, we design an in-memory multiplication algorithm based on the carry-save add-shift (CSAS) technique. Finally, we develop a novel stateful full-adder that significantly improves the state-of-the-art (FELIX) design. These contributions constitute MultPIM, a multiplier that reduces state-of-the-art time complexity from quadratic to linear-log. For 32-bit numbers, MultPIM improves latency by an additional 4.2x over RIME, while even slightly reducing area overhead. Furthermore, we optimize MultPIM for full-precision matrix-vector multiplication and improve latency by 25.5x over FloatPIM matrix-vector multiplication.

关键词： Logic gates Memristors Partitioning algorithms Adders Transistors Resistance Clocks processing-in-memory memristor multiplying circuits parallel algorithms iterative algorithms

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PIMSim: A Flexible and Detailed processing-in-memory Simulator

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2019年第1期18卷 6-9页

作者： Xu, Sheng Chen, Xiaoming Wang, Ying Han, Yinhe Qian, Xuehai Li, Xiaowei Chinese Acad Sci Inst Comp Technol Beijing Peoples R China Univ Chinese Acad Sci Beijing 101408 Peoples R China Univ Southern Calif Los Angeles CA 90007 USA

With the advent of big data applications and new process technologies, Process-in-memory (PIM) attracts much attention in memory research as the architecture studies gradually shift from processors to heterogeneous aspects. How to achieve reliable and efficient PIM architecture modeling becomes increasingly urgent for the researchers, who want to experiment on critical issues from detailed implementations of their proposed PIM designs. This paper proposes PIMSim, a full-system and highly-configurable PIM simulator to facilitate circuit-, architecture-and system-level researches. PIMSim enables architectural simulation of PIM and implements three simulation modes to provide a wide range of speed/accuracy tradeoffs. It offers detailed performance and energy models to simulate PIM-enabled instructions, compiler, in-memory processing logic, various memory devices, and PIM coherence. PIMSim is open source and available at https://***/vineodd/PIMSim.

关键词： processing-in-memory simulator heterogeneous computing memory system

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