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检索条件"主题词=Processing-in-memory"

共 354 条记录，以下是81-90 订阅

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abstractPIM: Bridging the Gap Between processing-in-memory Technology and Instruction Set Architecture 28

abstractPIM: Bridging the Gap Between Processing-In-Memory T...

引用

IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)

作者： Eliahu, Adi Ben-Hur, Rotem Ronen, Ronny Kvatinsky, Shahar Technion Israel Inst Technol Andrew & Erna Viterbi Fac Elect Engn IL-3200003 Haifa Israel

ISBN: (纸本)9781728154091

The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this paper, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.

关键词： Memristor processing-in-memory RRAM stateful logic ISA

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Using Logging-on-Write to Improve Non-Volatile memory Checkpoints via processing-in-memory 35

Using Logging-on-Write to Improve Non-Volatile Memory Checkp...

引用

35th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Kruger, Kleber Pannain, Ricardo Azevedo, Rodolfo Univ Estadual Campinas Inst Comp Campinas Brazil

ISBN: (纸本)9798350305487

NVM architectures must keep consistent data in case of failures, a property called crash consistency. A common way to do so is by checkpoint mechanisms. However, most of the strategies developed have performance and usability problems. Among main limitations are non-software-transparent strategies, the addition of logging operations in the critical execution path, and increased writes to NVM, resulting in significant bandwidth usage between processor and memory. DONUTS solves these problems by a hardware mechanism that provides crash consistency via checkpoints integrated into cache replacement policy using processing-in-memory to perform logging operations. Its approach reduces writes from the processor's memory controller and the NVM external bandwidth usage but generates unnecessary log entries. This paper expands DONUTS to a multi-core scenario evaluating two processing-in-memory strategies. The first logs during read operations, and the second uses a new lazy strategy to log data exclusively on write operations when these operations are effectively needed. Finally, we compare runtime performance, log rate, energy consumption, and memory space. Results show that our new logging-on-write strategy maintained the DONUTS runtime performance but reduced energy consumption in multi-core applications by around 33% due to an average reduction of 42% in log operations. Also, the new strategy generates a checkpoint size 5x smaller than the previous system, maximizing the use of NVM. Compared to other systems, DONUTS presented an average overhead of 1% to 3% against up to 7% of previous software-transparent better-performing projects.

关键词： processing-in-memory in-memory computing non-volatile memory checkpointing crash consistency

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Heterogeneous memory Architecture Accommodating processing-in-memory on SoC For AIoT Applications 22

Heterogeneous Memory Architecture Accommodating Processing-I...

引用

27th Asia and South Pacific Design Automation Conference (ASP-DAC)

作者： Qiu, Kangyi Zhang, Yaojun Yan, Bonan Huang, Ru Peking Univ Inst Artificial Intelligence Beijing Peoples R China Peking Univ Sch Integrated Circuits Beijing Peoples R China Pimchip Technol Co Ltd Beijing Peoples R China

ISBN: (纸本)9781665421355

processing-in-memory (PIM) technologies is one of most promising candidates for AIoT applications due to its attractive characteristics, such as low computation latency, large throughput and high power efficiency. However, how to efficiently utilize PIM with System-on-Chip (SoC) architecture has been scarcely discussed. In this paper, we demonstrate a series of solution from hardware architecture to algorithm to maximize the benefits of PIM design. First, we propose a Heterogeneous memory Architecture (HMA) that facilitates the existing SoC with PIM via high-throughput on-chip buses. Then, based on given HMA structure, we also propose an HMA tensor mapping approach to partition tensors and deploy general matrix multiplication operations on PIM structures. Both HMA hardware and HMA tensor mapping approach harnesses the programmability of the mature embedded CPU solution stack and maximize the high efficiency of PIM technology. The whole HMA system can save 416x power as well as 44.6% design area compare with the latest accelerator solutions. The evaluation also shows that our design can reduce the operation latency by 430x and 11x for TinyML applications, compare with state-of-art baseline and PIM without optimization, respectively.

关键词： processing-in-memory Compute-In-memory SoC Programmable Architecture Hardware/Software Interface

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A Study of Data Layout in Multi-channel processing-in-memory Architecture 2018

A Study of Data Layout in Multi-channel Processing-In-Memory...

引用

7th International Conference on Software and Computer Applications (ICSCA)

作者： Jeong, Taeyang Choi, Duheon Han, Sangwoo Chung, Eui-Young Yonsei Univ Dept Elect & Elect Engn Seoul South Korea

ISBN: (纸本)9781450354141

In modern computing hardware, the performance gap between processor and memory is one of the most significant factors that limits overall performance improvement of computing system. Also, with the advent of multicore and manycore system, memory bandwidth per core is decreasing constantly. To solve this problem, recently, many researchers are interested in processing-in-memory (PIM). PIM is that processing elements are attached to memory-side, so near-memory-processing which is suitable for memory intensive application can be possible. Various researches studied PIM, but it was just single-channel memory system. In addition, PIM is a new architecture that is different with conventional computing system. Thus, common data layout cannot become optimal case for PIM. Optimal data layout is also needed to be studied. In this paper, we propose the multi-channel PIM architecture with PIM-to-PIM communication, because data that is needed to operate can be distributed over several channels. To utilize multi-channel PIM architecture properly, we also introduce data layout that can minimize the number of PIM-to-PIM communications which are overheads of the system and maximize parallelism to reduce execution time. We evaluate it about vector arithmetic operation. The result is that execution time is improved about 393% and compared to the worst case, in the optimal data layout.

关键词： processing-in-memory data layout multi-channel memory

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Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM based processing-in-memory Architecture

Optimizing Weight Mapping and Data Flow for Convolutional Ne...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Peng, Xiaochen Liu, Rui Yu, Shimeng Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ USA

ISBN: (纸本)9781728103976

Resistive random access memory (RRAM) based array architecture has been proposed for on-chip acceleration of convolutional neural networks (CNNs), where the array could be configured for dot-product computation in a parallel fashion by summing up the column currents. Prior processing-in-memory (PIM) designs unroll each 3D kernel of the convolutional layers into a vertical column of a large weight matrix, where the input data will be accessed multiple times. As a result, significant latency and energy are consumed in interconnect and buffer. In this paper, in order to maximize both weight and input data reuse for RRAM based PIM architecture, we propose a novel weight mapping method and the corresponding data flow which divides the kernels and assign the input data into different processing-elements (PEs) according to their spatial locations. The proposed design achieves similar to 65% save in latency and energy for interconnect and buffer, and yields overall 2.1x speed up and similar to 17% improvement in the energy efficiency in terms of TOPS/W for VGG-16 CNN, compared with the prior design based on the conventional mapping method.

关键词： non-volatile memory processing-in-memory machine learning deep neural network hardware accelerator

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abstractPIM: A Technology Backward-Compatible Compilation Flow for processing-in-memory 1

引用

28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Eliahu, Adi Ben-Hur, Rotem Ronen, Ronny Kvatinsky, Shahar Technion Israel Inst Technol IL-3200003 Haifa Israel

ISBN: (数字)9783030816414

ISBN: (纸本)9783030816414;9783030816407

The von Neumann architecture, in which the memory and the computation units are separated, demands massive data traffic between the memory and the CPU. To reduce data movement, new technologies and computer architectures have been explored. The use of memristors, which are devices with both memory and computation capabilities, has been considered for different processing-in-memory (PIM) solutions, including using memristive stateful logic for a programmable digital PIM system. Nevertheless, all previous work has focused on a specific stateful logic family, and on optimizing the execution for a certain target machine. These solutions require new compiler and compilation when changing the target machine, and provide no backward compatibility with other target machines. In this chapter, we present abstractPIM, a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target independent ISA and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler. Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other, and discuss the challenges associated with it, such as the increase in execution time.

关键词： Memristor processing-in-memory RRAM stateful logic ISA

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Thermal Simulation of processing-in-memory Devices using HotSpot 7.0 27

Thermal Simulation of Processing-in-Memory Devices using Hot...

引用

27th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)

作者： Han, Jun-Han West, Robert E. Skadron, Kevin Stan, Mircea R. Univ Virginia Dept Elect & Comp Engn Charlottesville VA 22904 USA Univ Virginia Dept Comp Sci Charlottesville VA 22904 USA

ISBN: (纸本)9781665418966

3D Integrated Circuits (3D ICs) offer many advantages over their 2D counterparts, such as increased bandwidth and energy efficiency, that has lead to the popularity of commercial products such as HBM and HMC. However, they also have well- known thermal challenges that need to be resolved before they can be integrated with high performance processors or processing in memory (PIM). Microfluidic cooling is a promising solution to these thermal challenges, but its associated design space is large enough and complex enough that we need a design space exploration tool. We extend HotSpot, an existing thermal simulator, to support flexible modeling and simulation of microfluidic cooling designs. We believe this tool will enable research into novel microfluidic cooling techniques, ultimately resulting in higher performance 3D ICs with reduced thermal constraints.

关键词： In-memory computing processing-in-memory 3D-IC 3D-memory thermal modeling microfluidic cooling thermal management

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PIMSYN: Synthesizing processing-in-memory CNN Accelerators

PIMSYN: Synthesizing Processing-in-memory CNN Accelerators

引用

27th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Li, Wanqian Sun, Xiaotian Wang, Xinyu Wang, Lei Han, Yinhe Chen, Xiaoming Chinese Acad Sci Inst Comp Technol Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9798350348606;9783981926385

processing-in-memory architectures have been regarded as a promising solution for CNN acceleration. Existing PIM accelerator designs rely heavily on the experience of experts and require significant manual design overhead. Manual design cannot effectively optimize and explore architecture implementations. In this work, we develop an automatic framework PIMSYN for synthesizing PIM-based CNN accelerators, which greatly facilitates architecture design and helps generate energy-efficient accelerators. PIMSYN can automatically transform CNN applications into execution workflows and hardware construction of PIM accelerators. To systematically optimize the architecture, we embed an architectural exploration flow into the synthesis framework, providing a more comprehensive design space. Experiments demonstrate that PIMSYN improves the power efficiency by several times compared with existing works.

关键词： processing-in-memory synthesis neural network accelerators

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Performance Evaluation of Video Analytics Workloads on Emerging processing-in-memory Architectures

Performance Evaluation of Video Analytics Workloads on Emerg...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Challapalle, Nagadastagiri Narayanan, Vijaykrishnan Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA

ISBN: (数字)9781665466059

ISBN: (纸本)9781665466059

Deep learning based artificial intelligence algorithms are widely deployed in the video analytics pipelines as they drastically reduce the need for manual analysis and achieve human-like accuracy. However, they have high compute memory/storage requirements due to ever increasing model architecture size and large volumes of data. processing-in-memory architectures are gaining prominence for efficient execution of deep learning workloads as they reduce the data movement bottlenecks by moving compute closer to the data. In this work, we present the system level analysis of processing-in-memory architectures across the memory hierarchy for the execution of deep learning algorithms in the video analytics workloads using the proposed SysPIM methodology. We compare processing-in-memory architectures at cache memory, main memory, and non-volatile memory in terms of their execution latency, energy consumption, and overall data movement for representative video analytics workloads.

关键词： video analytics processing-in-memory cache main memory non-volatile memory

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PIMFlow: Compiler and Runtime Support for CNN Models on processing-in-memory DRAM 2023

PIMFlow: Compiler and Runtime Support for CNN Models on Proc...

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21st ACM/IEEE International Symposium on Code Generation and Optimization (CGO)

作者： Shin, Yongwon Park, Juseong Cho, Sungjun Sung, Hyojin POSTECH Grad Sch AI Pohang South Korea POSTECH Dept Comp Sci & Engn Pohang South Korea

ISBN: (纸本)9798400701016

processing-in-memory (PIM) has evolved over decades into a feasible solution to addressing the exacerbating performance bottleneck with main memory by placing computational logic in or near memory. Recent proposals from DRAM manufacturers highlighted the HW constraint-aware design of PIM-enabled DRAM with specialized MAC logic, providing an order of magnitude speedup for memory-intensive operations in DL models. Although the main target for PIM acceleration did not initially include convolutional neural networks due to their high compute intensity, recent CNN models are increasingly adopting computationally lightweight implementation. Motivated by the potential for the software stack to enable CNN models on DRAM-PIM hardware without invasive changes, we propose PIMFlow, an end-to-end compiler and runtime support, to accelerate CNN models on a PIM-enabled GPU memory. PIMFlow transforms model graphs to create inter-node parallelism across GPU and PIM, explores possible task- and data-parallel execution scenarios for optimal execution time, and provides a code-generating back-end and execution engine for DRAM-PIM. PIMFlow achieves up to 82% end-to-end speedup and reduces energy consumption by 26% on average for CNN model inferences.

关键词： processing-in-memory CNN models

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