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检索条件"主题词=Program Control Structures"

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Run-time Requirement Enforcement for Loop programs on Processor Arrays 18

Run-time Requirement Enforcement for Loop Programs on Proces...

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16th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)

作者： Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781538661956

Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption. To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement: at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives. Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality: 1) architecture-specific reduction by solving for parts of the mapping from the requirements, and 2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied. We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called tightly coupled processor arrays (TCPAs) and demonstrate their effectiveness with a case study. The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy.

关键词： embedded systems Linux multiprocessing systems parallel processing power aware computing program compilers program control structures reconfigurable architectures power aware computing program control structures Runtime Loops compilers Multiprocessing systems Reconfigurable architectures Contraceptive Coil Linux PARALLEL PROCESSING (COMPUTERS) Embedded systems MAPPING(MATHEMATICAL) ARRAY PROCESSORS enforcement

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Automatic Cluster Parallelization and Minimizing Communication via Selective Data Replication

Automatic Cluster Parallelization and Minimizing Communicati...

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IEEE High Performance Extreme Computing Conference (HPEC)

作者： Tavarageri, Sanket Meister, Benoit Baskaran, Muthu Pradelle, Benoit Henretty, Tom Konstantinidis, Athanasios Johnson, Ann Lethin, Richard Reservoir Labs 632 Broadway New York NY 10012 USA

ISBN: (纸本)9781467392860

The technology scaling has initiated two distinct trends that are likely to continue into future: first, the increased parallelism in hardware and second, the increasing performance and energy cost of communication relative to computation. Both of the above trends call for development of compiler and runtime systems to automatically parallelize programs and reduce communication in parallel computations to achieve the desired high performance in an energy-efficient fashion. In this paper, we propose the design of an integrated compiler and runtime system that auto-parallelizes loop-nests to clusters and, a novel communication avoidance method that reduces data movement between processors. Communication minimization is achieved via data replication: data is replicated so that a larger share of the whole data set may be mapped to a processor and hence, non-local memory accesses reduced. Experiments on a number of benchmarks show the effectiveness of the approach.

关键词： data handling parallel programming parallelising compilers power aware computing program control structures storage management automatic cluster parallelization automatic program parallelization communication avoidance method communication minimization compiler energy efficiency hardware parallelism loop-nest autoparallelization nonlocal memory access parallel computation processor data movement runtime system selective data replication technology scaling Arrays Benchmark testing Complexity theory Memory management Minimization program processors Runtime

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Verification of protocol specifications with separation logic 11

Verification of protocol specifications with separation logi...

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11th IEEE International Conference on Intelligent Computer Communication and Processing (ICCP)

作者： Kiss, Tibor Craciun, Florin Pary, Bazil Univ Babes Bolyai Fac Math & Comp Sci Dept Comp Sci R-3400 Cluj Napoca Romania

ISBN: (纸本)9781467382007

Despite their popularity, distributed programs remain a major challenge for the computer software verification. The need for methods for assuring safe interactions in such software systems is recognized. In the last few years, several new approaches have been proposed to solve the problem. Recent works have focused on developing behavior type systems to enforce the correct implementation of protocols, but this type systems are developed for languages with first class primitives for linear communication channels and communication-oriented control flow. In general for GPLs (general purpose programming languages), it is difficult to guarantee the correct implementation of protocol. In this paper, we propose to present an automated verification mechanism to ensure the protocol implementation correctness with respect to a session type specification. To support automatic verification, we design an entailment checking procedure which can handle the verification of a general purpose imperative programming language. Our theory establishes a framework for semantically precise enforcement of protocols, by extending the Separation Logic static analysis technique with a protocol verification mechanism.

关键词： distributed processing formal specification program control structures program diagnostics program verification GPLs automated verification mechanism automatic verification behavior type systems communication-oriented control flow computer software verification distributed programs entailment checking procedure general purpose programming languages imperative programming language linear communication channels protocol implementation correctness protocol specification verification protocol verification mechanism separation logic static analysis technique session type specification Communication channels Computer languages Protocols Safety Software Standards Switches Distributed software Computer programming Languages Communication channels protocols program control structures analysis programme program verification Distributed processing Switches computer software Protocol verification Verification Consumer safety safety Formal specifications

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Compiling HPC Kernels for the REDEFINE CGRA 17

Compiling HPC Kernels for the REDEFINE CGRA

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Madhu, Kavitha T. Das, Saptarsi Nalesh, S. Nandy, S. K. Narayan, Ranjani Indian Inst Sci CAD Lab Bangalore Karnataka India Morphing Machines Pvt Ltd Bangalore Karnataka India

ISBN: (纸本)9781479989379

In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communicate through messages. REDEFINE offers the ability to exploit high degree of coarse-grain and pipeline parallelism. The CEs in REDEFINE are enhanced with reconfigurable macro data-paths called HyperCells that enable exploitation of fine-grain and pipeline parallelism at the level of basic instructions in static dataflow order. Application kernels that exhibit regularity in computations and memory accesses such as affine loop nests benefit from the architecture of HyperCell [1], [2]. The proposed compilation flow aims at exposing high degree of parallelism in loop nests in HPC application kernels using polyhedral analysis and generates meta-data to effectively utilize the computational resources in HyperCells. Memory is explicitly managed through compiler's assistance. We address the compilation challenges such as partitioning with load balancing, mapping and scheduling computations and management of operand data while targeting multiple HyperCells in the REDEFINE architecture. The proposed solution scales well meeting the performance objectives of HPC computing.

关键词： data flow computing parallel architectures program compilers program control structures reconfigurable architectures storage management HPC application kernels HPC computing HPC kernels HyperCell architecture REDEFINE CGRA REDEFINE architecture REDEFINE coarse-grain reconfigurable architecture affine loop nests coarse-grain degree compilation flow compiler assistance computational resources compute elements load balancing mapping computation memory accesses memory management operand data management pipeline parallelism polyhedral analysis reconfigurable macro data paths scalable macro-dataflow machine scheduling computation static dataflow order Bandwidth Computer architecture Fabrics Kernel Parallel processing Pipelines Synchronization Architecture CGRA Compiler HPC Loop compilers Store management Coarse-grained Reconfigurable Architecture High Performance Computing program control structures Reconfigurable architectures pipeline Loops Parallel architectures Computer Architecture Load balancing Contraceptive Coil Building construction ARCHITECTURE PARALLEL PROCESSING (COMPUTERS)

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Extraction of Kahn Process Networks from While Loops in Embedded Software 17

Extraction of Kahn Process Networks from While Loops in Embe...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Aguilar, Miguel Angel Eusse, Juan Fernando Leupers, Rainer Ascheid, Gerd Odendahl, Maximilian Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany

ISBN: (纸本)9781479989379

Many embedded applications such as multimedia, signal processing and wireless communications present a streaming processing behavior. In order to take full advantage of modern multi-and many-core embedded platforms, these applications have to be parallelized by describing them in a given parallel Model of Computation (MoC). One of the most prominent MoCs is Kahn Process Network (KPN) as it allows to express multiple forms of parallelism and it is suitable for efficient mapping and scheduling onto parallel embedded platforms. However, describing streaming applications manually in a KPN is a challenging task. Especially, since they spend most of their execution time in loops with unbounded number of iterations. These loops are in several cases implemented as while loops, which are difficult to analyze. In this paper, we present an approach to guide the derivation of KPNs from embedded streaming applications dominated by multiple types of while loops. We evaluate the applicability of our approach on an eight DSP core commercial embedded platform using realistic benchmarks. Results measured on the platform showed that we are able to speedup sequential benchmarks on average by a factor up to 4.3x and in the best case up to 7.7x. Additionally, to evaluate the effectiveness of our approach, we compared it against a state-of-the-art parallelization framework.

关键词： digital signal processing chips embedded systems parallel processing program control structures DSP core embedded platform KPN Kahn process network extraction MoC embedded software embedded streaming applications execution time many-core embedded platforms multicore embedded platforms parallel embedded platforms parallel model-of-computation parallelized applications sequential benchmarks while loops Computational modeling Data mining Long Term Evolution Parallel processing Runtime Switches Uplink DSP Kahn Process Networks MPSoCs Parallelization While Loops PARALLEL PROCESSING (COMPUTERS) Embedded software digital signal processing chips Loops program control structures execution time Long Term Evolution parallelization Runtime up link Digital signal processing Desmoplakin Gene Computational modeling Embedded systems Switches

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TRACO: An Automatic Loop Nest Parallelizer for Numerical Applications

TRACO: An Automatic Loop Nest Parallelizer for Numerical App...

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3rd International Conference on Innovative Network Systems and Applications (iNetSApp) held in conjunction with Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Palkowski, Marek Klimek, Tomasz Bielecki, Wlodzimierz West Pomeranian Univ Technol Szczecin Ul Zolnierska 49 PL-71210 Szczecin Poland

ISBN: (纸本)9788360810668

We present the source-to-source TRACO compiler allowing for increasing program locality and parallelizing arbitrarily nested loop sequences in numerical applications. Algorithms for generation of tiled code and extracting synchronization-free slices composed of tiles are presented. Parallelism of arbitrary nested loops is obtained by creating a kernel of computations represented in the OpenMP standard to be executed independently on many CPUs. We consider benchmarks, typical from compute-intensive sequences of algebra operations or numerical computation from industry and engineering. The speed-up of programs generated by TRACO are discussed. Related compilers and techniques are considered. Future work is outlined.

关键词： application program interfaces mathematics computing numerical analysis parallel algorithms program compilers program control structures program slicing synchronisation CPUs OpenMP standard algebra operations arbitrary nested loop sequence parallelism automatic loop nest parallelizer compute-intensive sequences program locality source-to-source TRACO compiler synchronization-free slice extraction tiled code generation Benchmark testing Computational modeling Kernel Mathematical model Multicore processing Parallel processing Schedules

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Flattening-based Mapping of Imperfect Loop Nests for CGRAs 14

Flattening-based Mapping of Imperfect Loop Nests for CGRAs

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International Conference on Hardware / Software Codesign and System Synthesis (CODES+ISSS)

作者： Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781450330510

For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, are either designed for perfectly nested loops only, or expensive and inflexible. Efficient CGRA mapping of imperfect loops with arbitrary nesting depth still remains a challenge. In this paper we propose a compiler-hardware co-operative approach that is flexible and yet able to generate efficient mappings for imperfect nested loops. It is based on loop flattening, but to mitigate the negative impact of flattening we combine loop fission and a light-weight architecture extension that is designed to accelerate common operation patterns appearing frequently in flattened loops. Our experimental results using imperfect loops from multimedia and DSP domains demonstrate that our special operations can cover a large portion of nested loop operations, improve performance of nested loops by nearly 30% over using loop flattening only, and achieve near-ideal executions on CGRAs for imperfect loops.

关键词： parallel processing program compilers program control structures CGRA DSP domains GP-GPUs coarse-grained reconfigurable architectures compiler-hardware cooperative approach flattening-based loop nest mapping light-weight architecture extension loop accelerators loop fission loop flattening multimedia domains nested loop mapping parallelism source Arrays Kernel Nickel Pipeline processing Registers Coarse-grained Reconfigurable Architecture Loops program control structures Imperfect Pipeline processing compilers Registers PARALLEL PROCESSING (COMPUTERS) Nickel Contraceptive Coil FLATTENING Kernel MAPPING(MATHEMATICAL)

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Building Development Tools Interactively using the EKEKO Meta-programming Library

Building Development Tools Interactively using the EKEKO Met...

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Software Evolution Week / IEEE Conference on Software Maintenance, Reengineering, and Reverse Engineering (CSMR-WCRE)

作者： De Roover, Coen Stevens, Reinout Vrije Univ Brussel Software Languages Lab Brussels Belgium

ISBN: (纸本)9781479937523

EKEKO is a Clojure library for applicative logic meta-programming against an Eclipse workspace. EKEKO has been applied successfully to answering program queries (e.g., "does this bug pattern occur in my code?"), to analyzing project corpora (e.g., "how often does this API usage pattern occur in this corpus?"), and to transforming programs (e.g., "change occurrences of this pattern as follows") in a declarative manner. These applications rely on a seamless embedding of logic queries in applicative expressions. While the former identify source code of interest, the latter associate error markers with, compute statistics about, or rewrite the identified source code snippets. In this paper, we detail the logic and applicative aspects of the EKEKO library. We also highlight key choices in their implementation. In particular, we demonstrate how a causal connection with the Eclipse infrastructure enables building development tools interactively on the Clojure read-eval-print loop.

关键词： application program interfaces logic programming program control structures program debugging query processing software libraries source code (software) API usage pattern Clojure library Clojure read-eval-print loop EKEKO metaprogramming library Eclipse infrastructure Eclipse workspace applicative logic metaprogramming building development tools error markers logic queries program query answering program transformation project corpora analysis source code snippet identification Buildings Computational modeling Java Libraries Logic programming Vectors Visualization

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Deferring Accelerator Offloading Decisions to Application Runtime

Deferring Accelerator Offloading Decisions to Application Ru...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Vaz, Gavin Riebler, Heinrich Kenter, Tobias Plessl, Christian Univ Paderborn Dept Comp Sci D-33098 Paderborn Germany

ISBN: (纸本)9781479959440

Reconfigurable architectures provide an opportunity to accelerate a wide range of applications, frequently by exploiting data-parallelism, where the same operations are homogeneously executed on a (large) set of data. However, when the sequential code is executed on a host CPU and only data-parallel loops are executed on an FPGA coprocessor, a sufficiently large number of loop iterations (trip counts) is required, such that the control-and data-transfer overheads to the coprocessor can be amortized. However, the trip count of large data-parallel loops is frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code both for the CPU and the coprocessor, and to defer the decision where to execute the appropriate code to the runtime of the application when the trip count of the loop can be determined just at runtime. We demonstrate how an LLVM compiler based toolflow can automatically insert appropriate decision blocks into the application code. Analyzing popular benchmark suites, we show that this kind of runtime decisions is often applicable. The practical feasibility of our approach is demonstrated by a toolflow that automatically identifies loops suitable for vectorization and generates code for the FPGA coprocessor of a Convey HC-1. The toolflow adds decisions based on a comparison of the runtime-computed trip counts to thresholds for specific loops and also includes support to move just the required data to the coprocessor. We evaluate the integrated toolflow with characteristic loops executed on different input data sizes.

关键词： coprocessors field programmable gate arrays program compilers program control structures reconfigurable architectures CPU Convey HC-1 FPGA coprocessor LLVM compiler based toolflow accelerator offloading decision application runtime compile time control-transfer overhead data-parallelism data-transfer overhead decision block large data-parallel loop loop iteration reconfigurable architecture runtime-computed trip count sequential code Benchmark testing Coprocessors Field programmable gate arrays Libraries Memory management Runtime Vectors

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Property Directed Invariant Refinement for program Verification

Property Directed Invariant Refinement for Program Verificat...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Welp, Tobias Kuehlmann, Andreas Univ Calif Berkeley Berkeley CA 94720 USA Coverity Inc San Francisco CA USA

ISBN: (纸本)9783981537024

We present a novel, sound, and complete algorithm for deciding safety properties in programs with static memory allocation. The new algorithm extends the program verification paradigm using loop invariants presented in [1] with a counterexample guided abstraction refinement (CEGAR) loop [2] where the refinement is achieved by strengthening loop invariants using the QF_BV generalization of Property Directed Reachability (PDR) discussed in [3, 4]. We compare the algorithm with other approaches to program verification and report experimental results.

关键词： embedded systems program control structures program verification storage allocation QF BV generalization counterexample guided abstraction refinement loop loop invariants program verification paradigm property directed invariant refinement property directed reachability static memory allocation Abstracts Algorithm design and analysis Bismuth Interpolation Resource management Safety Software

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