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检索条件"主题词=Program Control Structures"
45 条 记 录,以下是1-10 订阅
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Run-time Requirement Enforcement for Loop programs on Processor Arrays  18
Run-time Requirement Enforcement for Loop Programs on Proces...
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16th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
作者: Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany
Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might ... 详细信息
来源: 评论
Automatic Cluster Parallelization and Minimizing Communication via Selective Data Replication
Automatic Cluster Parallelization and Minimizing Communicati...
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IEEE High Performance Extreme Computing Conference (HPEC)
作者: Tavarageri, Sanket Meister, Benoit Baskaran, Muthu Pradelle, Benoit Henretty, Tom Konstantinidis, Athanasios Johnson, Ann Lethin, Richard Reservoir Labs 632 Broadway New York NY 10012 USA
The technology scaling has initiated two distinct trends that are likely to continue into future: first, the increased parallelism in hardware and second, the increasing performance and energy cost of communication re... 详细信息
来源: 评论
Verification of protocol specifications with separation logic  11
Verification of protocol specifications with separation logi...
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11th IEEE International Conference on Intelligent Computer Communication and Processing (ICCP)
作者: Kiss, Tibor Craciun, Florin Pary, Bazil Univ Babes Bolyai Fac Math & Comp Sci Dept Comp Sci R-3400 Cluj Napoca Romania
Despite their popularity, distributed programs remain a major challenge for the computer software verification. The need for methods for assuring safe interactions in such software systems is recognized. In the last f... 详细信息
来源: 评论
Compiling HPC Kernels for the REDEFINE CGRA  17
Compiling HPC Kernels for the REDEFINE CGRA
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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)
作者: Madhu, Kavitha T. Das, Saptarsi Nalesh, S. Nandy, S. K. Narayan, Ranjani Indian Inst Sci CAD Lab Bangalore Karnataka India Morphing Machines Pvt Ltd Bangalore Karnataka India
In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communica... 详细信息
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Extraction of Kahn Process Networks from While Loops in Embedded Software  17
Extraction of Kahn Process Networks from While Loops in Embe...
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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)
作者: Aguilar, Miguel Angel Eusse, Juan Fernando Leupers, Rainer Ascheid, Gerd Odendahl, Maximilian Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany
Many embedded applications such as multimedia, signal processing and wireless communications present a streaming processing behavior. In order to take full advantage of modern multi-and many-core embedded platforms, t... 详细信息
来源: 评论
TRACO: An Automatic Loop Nest Parallelizer for Numerical Applications
TRACO: An Automatic Loop Nest Parallelizer for Numerical App...
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3rd International Conference on Innovative Network Systems and Applications (iNetSApp) held in conjunction with Federated Conference on Computer Science and Information Systems (FedCSIS)
作者: Palkowski, Marek Klimek, Tomasz Bielecki, Wlodzimierz West Pomeranian Univ Technol Szczecin Ul Zolnierska 49 PL-71210 Szczecin Poland
We present the source-to-source TRACO compiler allowing for increasing program locality and parallelizing arbitrarily nested loop sequences in numerical applications. Algorithms for generation of tiled code and extrac... 详细信息
来源: 评论
Flattening-based Mapping of Imperfect Loop Nests for CGRAs  14
Flattening-based Mapping of Imperfect Loop Nests for CGRAs
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International Conference on Hardware / Software Codesign and System Synthesis (CODES+ISSS)
作者: Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea
For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, a... 详细信息
来源: 评论
Building Development Tools Interactively using the EKEKO Meta-programming Library
Building Development Tools Interactively using the EKEKO Met...
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Software Evolution Week / IEEE Conference on Software Maintenance, Reengineering, and Reverse Engineering (CSMR-WCRE)
作者: De Roover, Coen Stevens, Reinout Vrije Univ Brussel Software Languages Lab Brussels Belgium
EKEKO is a Clojure library for applicative logic meta-programming against an Eclipse workspace. EKEKO has been applied successfully to answering program queries (e.g., "does this bug pattern occur in my code?&quo... 详细信息
来源: 评论
Deferring Accelerator Offloading Decisions to Application Runtime
Deferring Accelerator Offloading Decisions to Application Ru...
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2014 International Conference on Reconfigurable Computing and FAGAs
作者: Vaz, Gavin Riebler, Heinrich Kenter, Tobias Plessl, Christian Univ Paderborn Dept Comp Sci D-33098 Paderborn Germany
Reconfigurable architectures provide an opportunity to accelerate a wide range of applications, frequently by exploiting data-parallelism, where the same operations are homogeneously executed on a (large) set of data.... 详细信息
来源: 评论
Property Directed Invariant Refinement for program Verification
Property Directed Invariant Refinement for Program Verificat...
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Design, Automation and Test in Europe Conference and Exhibition (DATE)
作者: Welp, Tobias Kuehlmann, Andreas Univ Calif Berkeley Berkeley CA 94720 USA Coverity Inc San Francisco CA USA
We present a novel, sound, and complete algorithm for deciding safety properties in programs with static memory allocation. The new algorithm extends the program verification paradigm using loop invariants presented i... 详细信息
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