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26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014

作者： Santiago, Leandro Marzulo, Leandro A.J. Goldstein, Brunno F. Alves, Tiago A.O. França, Felipe M.G. Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil

ISBN: (纸本)9781479970148

Dynamic Dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, incremented as they go through the loop. Instruction execution is triggered when all input operand with the same tag become available. However, this traditional tagging mechanism often requires the generation of several control instructions to manipulate tags and guarantee the correct matching. To address this problem, this work presents Stack- Tagged Dataflow, a tagging mechanism that uses stacks of tags to reduce control overheads in dataflow, while isolating context from different nested loops. Push instructions at the beginning of loops will create a new context, while Pop instructions, at the end of the loop, will restore the original context tags. Experimental results show that Stack-Tagged Dataflow is a viable solution, suggesting that a hybrid compiling approach can be used to enable Stack- Tags only when needed. © 2014 IEEE.

关键词： data flow computing program control structures context isolation dataflow control overhead reduction nested loops pop instructions push instructions stack-tagged dataflow tagging mechanism Assembly Computer architecture Context Libraries Parallel processing Tagging Virtual machining Dataflow Parallel programming Stack Tag data flow TAGGING program control structures virtual machines Parallel programming Computer Architecture Furnace conveyors PARALLEL PROCESSING (COMPUTERS) Loops Libraries assemblies NESTED LOOPS virtual machining instruction

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Generalized Hankel Interaction Index Array for control Structure Selection for Discrete-Time MIMO Bilinear Processes and Plants

Generalized Hankel Interaction Index Array for Control Struc...

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IEEE Annual Conference on Decision and control

作者： Hamid Reza Shaker Maryamsadat Tahavori Center for Smart Energy Solutions University of Southern Denmark Odense Denmark

ISBN: (纸本)9781467360890

The control technology has been orientated towards decentralized and partially decentralized control strategies. To ensure the success of a decentralized or a partially decentralized control in practice, the first necessary step is to determine a suitable control structure. The control structure selection which is the task of selecting suitable input and output pairs for control design is therefore very important. This paper focuses on control structure selection for discrete-time MIMO bilinear systems. The generalized cross-gramian is introduced in this paper for discrete-time bilinear processes and plants. The existence of the generalized cross-gramian is studied and it is shown that if the cross-gramian exists, it can be obtained by solving a generalized Sylvester equation. To solve the generalized Sylvester equation in a computationally efficient way, an iterative method is developed and presented. The generalized cross-gramians are computed for all SISO subsystems of the discrete-time MIMO bilinear systems. These gramians are used to build the generalized Hankel Interaction Index Array which is used for control structure selection. The proposed method for control structure selection is among the few methods supporting bilinear processes and plants, enjoys the advantages of gramian based methods and it is more efficient in terms of computations compared to its counterparts.

关键词： control Architecture Decentralized program control structures discrete-time bilinearity Hankel control technology

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program analysis too loopy? Set the loops aside

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IET SOFTWARE 2013年第3期7卷 131-149页

作者： Larson, Eric Seattle Univ Seattle WA 98122 USA

Among the many obstacles to efficient and sound program analysis, loops may be the most prevalent. In program analyses that traverse paths, loops introduce a variable, possibly infinite and number of paths. This study assesses the potential of a program analysis technique that analyses loops separately and replaces the loop with a summary, similar to how many analyses use summaries for interprocedural analysis. This study is conducted by comparing the path counts when loops are analysed separately to a baseline path count where loops are traversed at most once. Although the number of paths is decreased in many cases, the magnitude of the decrease is typically not sufficient for long, complex functions. In addition, loops are classified by the task they perform, analysed using the number of paths as an estimate of their complexity and further inspected for programming elements that may make loop analysis more difficult. Of the 2869 loops used in this study, 84% of the loops have fewer than ten paths and only 1.3% have more than 10 000 paths. Nearly 60% of the loops traverse arrays or strings and roughly half of the loops contain a function call.

关键词： program control structures program diagnostics program analysis technique interprocedural analysis baseline path count complex functions programming elements loop analysis loop traverse arrays loop traverse strings function call program control structures program diagnostics program analysis technique interprocedural analysis baseline path count complex functions programming elements loop analysis loop traverse arrays loop traverse strings function call

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Toddler: Detecting Performance Problems via Similar Memory-Access Patterns

Toddler: Detecting Performance Problems via Similar Memory-A...

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35th International Conference on Software Engineering (ICSE)

作者： Nistor, Adrian Song, Linhai Marinov, Darko Lu, Shan Univ Illinois Champaign IL 61820 USA Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467330763

Performance bugs are programming errors that create significant performance degradation. While developers often use automated oracles for detecting functional bugs, detecting performance bugs usually requires time-consuming, manual analysis of execution profiles. The human effort for performance analysis limits the number of performance tests analyzed and enables performance bugs to easily escape to production. Unfortunately, while profilers can successfully localize slow executing code, profilers cannot be effectively used as automated oracles. This paper presents TODDLER, a novel automated oracle for performance bugs, which enables testing for performance bugs to use the well established and automated process of testing for functional bugs. TODDLER reports code loops whose computation has repetitive and partially similar memory-access patterns across loop iterations. Such repetitive work is likely unnecessary and can be done faster. We implement TODDLER for Java and evaluate it on 9 popular Java codebases. Our experiments with 11 previously known, real-world performance bugs show that TODDLER finds these bugs with a higher accuracy than the standard Java profiler. Using TODDLER, we also found 42 new bugs in six Java projects: Ant, Google Core Libraries, JUnit, Apache Collections, JDK, and JFreeChart. Based on our bug reports, developers so far fixed 10 bugs and confirmed 6 more as real bugs.

关键词： Java program control structures program debugging program testing software performance evaluation

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Quantitative Reasoning for Proving Lock-Freedom 13

Quantitative Reasoning for Proving Lock-Freedom

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28th Annual IEEE/ACM Symposium on Logic in Computer Science (LICS)

作者： Hoffmann, Jan Marmar, Michael Shao, Zhong Yale Univ New Haven CT 06520 USA

ISBN: (纸本)9781479904136

This article describes a novel quantitative proof technique for the modular and local verification of lock-freedom. In contrast to proofs based on temporal rely-guarantee requirements, this new quantitative reasoning method can be directly integrated in modern program logics that are designed for the verification of safety properties. Using a single formalism for verifying memory safety and lock-freedom allows a combined correctness proof that verifies both properties simultaneously. This article presents one possible formalization of this quantitative proof technique by developing a variant of concurrent separation logic (CSL) for total correctness. To enable quantitative reasoning, CSL is extended with a predicate for affine tokens to account for, and provide an upper bound on the number of loop iterations in a program. Lock-freedom is then reduced to total-correctness proofs. Quantitative reasoning is demonstrated in detail, both informally and formally, by verifying the lock-freedom of Treiber's non-blocking stack. Furthermore, it is shown how the technique is used to verify the lock-freedom of more advanced shared-memory data structures that use elimination-backoff schemes and hazard-pointers.

关键词： concurrency theory formal verification inference mechanisms program control structures shared memory systems temporal logic theorem proving

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Path-Sensitive Resource Analysis Compliant with Assertions

Path-Sensitive Resource Analysis Compliant with Assertions

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International Conference on Embedded Software (EMSOFT)

作者： Chu, Duc-Hiep Jaffar, Joxan Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781479914432

We consider the problem of bounding the worst-case resource usage of programs, where assertions about valid program executions may be enforced at selected program points. It is folklore that to be precise, path-sensitivity (up to loops) is needed. This entails unrolling loops in the manner of symbolic simulation. To be tractable, however, the treatment of the individual loop iterations must be greedy in the sense once analysis is finished on one iteration, we cannot backtrack to change it. We show that under these conditions, enforcing assertions produces unsound results. The fundamental reason is that complying with assertions requires the analysis to be fully sensitive (also with loops) wrt. the assertion variables. We then present an algorithm where the treatment of each loop is separated in two phases. The first phase uses a greedy strategy in unrolling the loop. This phase explores what is conceptually a symbolic execution tree, which is of enormous size, while eliminates infeasible paths and dominated paths that guaranteed not to contribute to the worst case bound. A compact representation is produced at the end of this phase. Finally, the second phase attacks the remaining problem, to determine the worst-case path in the simplified tree, excluding all paths that violate the assertions from bound calculation. Scalability, in both phases, is achieved via an adaptation of a dynamic programming algorithm.

关键词： dynamic programming iterative methods program control structures program diagnostics trees (mathematics)

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Automatic Enhanced CDFG Generation based on Runtime Instrumentation

Automatic Enhanced CDFG Generation based on Runtime Instrume...

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IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD)

作者： Yuan, Zhongda Ma, Yuchun Bian, Jinian Zhao, Kang Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781467360852;9781467360845

control and Data Flow Graph (CDFG) is a universal description of program behavior, which is widely used in the co-design of software and hardware. The derivation of CDFG has been done mostly by manually or automatically analyzing corresponding source code, which makes this process time-consuming, error-prone and incomplete. In this paper, we proposed an automated design flow based on runtime instrumentation to generate Enhanced CDFG (ECDFG) with additional runtime information. Though the approach of runtime instrumentation is widely used in software debugging to analyze the program with the accurate runtime information, it is rarely used in software and hardware co-design due to the huge trace data and processing overhead. To overcome the bottle neck of the runtime instrumentation approach, Parallel Background Event Logger is proposed to compress and save the huge amount of trace data. Hierarchical loop structures are detected by intersecting reachable set and backward reachable set. Precise data dependency information is deducted by an address based analytical method named Shower Line Algorithm. With these algorithms and techniques, a set of automatic design tools are implemented to collect runtime events, identify nested and implicit loops and deduct data dependance between modules. Exemplar results demonstrated that Enhanced CDFGs for various programs can be generated correctly with acceptable overhead.

关键词： data flow graphs hardware-software codesign instrumentation parallel processing program control structures program debugging source coding

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Affine Transformations for Communication and Reconfiguration Optimization of Loops on CGRAs

Affine Transformations for Communication and Reconfiguration...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Liu, Dajiang Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua Univ Res Ctr Mobile Comp Beijing 100084 Peoples R China Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781467357623;9781467357609

A coarse-grained reconfigurable architecture (CGRA) is typically a hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many compute-intensive applications (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. However, communication volume and reconfiguration cost are two bottlenecks for the performance of RPUs. Therefore, loop transformations to break through the bottlenecks and tap the potentials of RPU would be of much significance. In this paper, an automatic loop transformation approach for RPUs is proposed, where the communication cost and reconfiguration cost are under a joint consideration. Experimental results show that our scheme can save up to 22.7% of execution time on average on partial differential equation (PDE) solver kernels compared with the approach just considering communication cost, and performs much better than the loop unrolling scheme on a great majority of loop kernels. Also, run-time complexity is acceptable for the practical cases.

关键词： affine transforms microprocessor chips operating system kernels optimisation partial differential equations program control structures reconfigurable architectures

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Symbolic Parallelization of Loop programs for Massively Parallel Processor Arrays

Symbolic Parallelization of Loop Programs for Massively Para...

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IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Teich, Juergen Tanase, Alexandru Hannig, Frank Univ Erlangen Nurnberg Dept Comp Sci Nurnberg Germany

ISBN: (纸本)9781479904945;9781479904938

In this paper, we present a first solution to the unsolved problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This problem arises for loop programs for which the iterations shall be optimally scheduled on a processor array of unknown size at compile-time. Still, we show that it is possible to derive parameterized latency-optimal schedules statically by proposing two new program transformations: In the first step, the iteration space is tiled symbolically into orthotopes of parametrized extensions. The resulting tiled program is subsequently scheduled symbolically. Here, we show that the maximal number of potential optimal schedules is upper bounded by 2(n)n! where n is the dimension of the loop nest. However, the real number of optimal schedule candidates being much less than this. At run-time, once the size of the processor array becomes known, simple comparisons of latency-determining expressions finally steer which of these schedules will be dynamically activated and the corresponding program configuration executed on the resulting processor array so to avoid any further run-time optimization or expensive re-compilations.

关键词： parallel processing parallelising compilers processor scheduling program control structures

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Hybrid Relation Calculus

Hybrid Relation Calculus

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18th International Conference on Engineering of Complex Computer Systems (ICECCS)

作者： He, Jifeng E China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China

form only given. Hybrid systems are composed by continuous physical component and discrete control component where the system state evolves over time according to interacting law of discrete and continuous dynamics. C... 详细信息

ISBN: (纸本)9780769550077

关键词： automata theory parallel languages parallel programming program control structures relational algebra

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