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检索条件"主题词=Program Control Structures"

共 45 条记录，以下是11-20 订阅

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Toddler: Detecting Performance Problems via Similar Memory-Access Patterns

Toddler: Detecting Performance Problems via Similar Memory-A...

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35th International Conference on Software Engineering (ICSE)

作者： Nistor, Adrian Song, Linhai Marinov, Darko Lu, Shan Univ Illinois Champaign IL 61820 USA Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467330763

Performance bugs are programming errors that create significant performance degradation. While developers often use automated oracles for detecting functional bugs, detecting performance bugs usually requires time-consuming, manual analysis of execution profiles. The human effort for performance analysis limits the number of performance tests analyzed and enables performance bugs to easily escape to production. Unfortunately, while profilers can successfully localize slow executing code, profilers cannot be effectively used as automated oracles. This paper presents TODDLER, a novel automated oracle for performance bugs, which enables testing for performance bugs to use the well established and automated process of testing for functional bugs. TODDLER reports code loops whose computation has repetitive and partially similar memory-access patterns across loop iterations. Such repetitive work is likely unnecessary and can be done faster. We implement TODDLER for Java and evaluate it on 9 popular Java codebases. Our experiments with 11 previously known, real-world performance bugs show that TODDLER finds these bugs with a higher accuracy than the standard Java profiler. Using TODDLER, we also found 42 new bugs in six Java projects: Ant, Google Core Libraries, JUnit, Apache Collections, JDK, and JFreeChart. Based on our bug reports, developers so far fixed 10 bugs and confirmed 6 more as real bugs.

关键词： Java program control structures program debugging program testing software performance evaluation

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Non-Termination Analysis of Linear Loop programs with Conditionals

Non-Termination Analysis of Linear Loop Programs with Condit...

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International Conference on Advanced Software Engineering and Its Applications

作者： Bi, Zhongqin Shan, Meijing Wu, Bin E China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai 200062 Peoples R China

ISBN: (纸本)9780769534329

Non-Termination analysis of loop programs plays a central role in many applications, especially in the field of safety critical softwares. This paper presents a method to analyze non-termination of linear programs with conditionals. We transform the linear loop programs with conditionals into the nested linear loop programs, and then check whether the inner loop terminates or not by the positive eigenvalues and their corresponding eigenvectors. If one of the inner loop in the nested linear loop is nonterminating, then the linear loop is nonterminating. Otherwise, we need to use ranking function or finite differences of expressions over transition systems to analyze the termination of the outer loop.

关键词： Linear Loop programs Non-Termination Analysis program Transform internal recycling program control structures Safety critical linear programming Finite differences Linear

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Impact on Reliability in the control-Flow of programs under Compiler Optimizations

Impact on Reliability in the Control-Flow of Programs under ...

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Brazilian Symposium on Computing System Engineering (SBESC)

作者： Parizi, Rafael Ferreira, Ronaldo Freitas, Alvaro Carro, Luigi Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781467357470;9780769549293

This paper evaluates the impact on reliability in the control-flow of programs that compiler optimizations incur in terms of fault coverage for the Automatic Correction of control-flow Errors technique. This technique was implemented in the LLVM framework, enabling the automated analysis of programs. In order to evaluate the efficiency of the technique of fault tolerance we performed a series of fault injection experiments using the MiBench benchmark suite as case study, measuring how individual and combined optimizations impact reliability.

关键词： error correction optimising compilers program control structures program diagnostics program testing software fault tolerance

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On Using LALP to Map an Audio Encoder/Decoder on FPGAs

On Using LALP to Map an Audio Encoder/Decoder on FPGAs

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Menotti, Ricardo Cardoso, Joao M. P. Fernandes, Marcio M. Marques, Eduardo Univ Tecnol Fed Parana Campo Mourao Brazil Univ Porto Fac Engn Dept Informat Engn Oporto Portugal Univ Fed Sao Carlos Dept Comp Sao Carlos SP Brazil Univ Sao Paulo Inst Ciencias Matemat & Comp Sao Paulo Brazil

ISBN: (纸本)9781424463916

This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. LALP is a domain specific language and its compilation framework aims to the direct mapping of algorithms originally described in a high-level language onto FPGAs. In particular, LALP focuses on loop pipelining, a key technique for the design of hardware accelerators. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware. We present experimental results showing significant performance gains using this approach, while still keeping the language syntax and semantics close to popular high level software languages, a desirable feature when considering time to market constraints. We believe the performance gains observed for the ADPCM implementation can be extended to other industrial applications relying on algorithms spending most of their execution time on loop structures, such signal and image processing.

关键词： ADPCM Decoder ADPCM Encoder FPGA LALP audio coding audio encoder/decoder codecs compilation framework data dependences direct algorithm mapping domain specific language field programmable gate arrays hardware accelerators high-level language industrial application kernels language semantics language syntax loop pipelining pipeline processing program compilers program control structures programmer interventions telecommunication computing

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Flattening-based Mapping of Imperfect Loop Nests for CGRAs 14

Flattening-based Mapping of Imperfect Loop Nests for CGRAs

引用

International Conference on Hardware / Software Codesign and System Synthesis (CODES+ISSS)

作者： Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781450330510

For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, are either designed for perfectly nested loops only, or expensive and inflexible. Efficient CGRA mapping of imperfect loops with arbitrary nesting depth still remains a challenge. In this paper we propose a compiler-hardware co-operative approach that is flexible and yet able to generate efficient mappings for imperfect nested loops. It is based on loop flattening, but to mitigate the negative impact of flattening we combine loop fission and a light-weight architecture extension that is designed to accelerate common operation patterns appearing frequently in flattened loops. Our experimental results using imperfect loops from multimedia and DSP domains demonstrate that our special operations can cover a large portion of nested loop operations, improve performance of nested loops by nearly 30% over using loop flattening only, and achieve near-ideal executions on CGRAs for imperfect loops.

关键词： parallel processing program compilers program control structures CGRA DSP domains GP-GPUs coarse-grained reconfigurable architectures compiler-hardware cooperative approach flattening-based loop nest mapping light-weight architecture extension loop accelerators loop fission loop flattening multimedia domains nested loop mapping parallelism source Arrays Kernel Nickel Pipeline processing Registers Coarse-grained Reconfigurable Architecture Loops program control structures Imperfect Pipeline processing compilers Registers PARALLEL PROCESSING (COMPUTERS) Nickel Contraceptive Coil FLATTENING Kernel MAPPING(MATHEMATICAL)

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Quantitative Reasoning for Proving Lock-Freedom 13

Quantitative Reasoning for Proving Lock-Freedom

引用

28th Annual IEEE/ACM Symposium on Logic in Computer Science (LICS)

作者： Hoffmann, Jan Marmar, Michael Shao, Zhong Yale Univ New Haven CT 06520 USA

ISBN: (纸本)9781479904136

This article describes a novel quantitative proof technique for the modular and local verification of lock-freedom. In contrast to proofs based on temporal rely-guarantee requirements, this new quantitative reasoning method can be directly integrated in modern program logics that are designed for the verification of safety properties. Using a single formalism for verifying memory safety and lock-freedom allows a combined correctness proof that verifies both properties simultaneously. This article presents one possible formalization of this quantitative proof technique by developing a variant of concurrent separation logic (CSL) for total correctness. To enable quantitative reasoning, CSL is extended with a predicate for affine tokens to account for, and provide an upper bound on the number of loop iterations in a program. Lock-freedom is then reduced to total-correctness proofs. Quantitative reasoning is demonstrated in detail, both informally and formally, by verifying the lock-freedom of Treiber's non-blocking stack. Furthermore, it is shown how the technique is used to verify the lock-freedom of more advanced shared-memory data structures that use elimination-backoff schemes and hazard-pointers.

关键词： concurrency theory formal verification inference mechanisms program control structures shared memory systems temporal logic theorem proving

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Verification of protocol specifications with separation logic 11

Verification of protocol specifications with separation logi...

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11th IEEE International Conference on Intelligent Computer Communication and Processing (ICCP)

作者： Kiss, Tibor Craciun, Florin Pary, Bazil Univ Babes Bolyai Fac Math & Comp Sci Dept Comp Sci R-3400 Cluj Napoca Romania

ISBN: (纸本)9781467382007

Despite their popularity, distributed programs remain a major challenge for the computer software verification. The need for methods for assuring safe interactions in such software systems is recognized. In the last few years, several new approaches have been proposed to solve the problem. Recent works have focused on developing behavior type systems to enforce the correct implementation of protocols, but this type systems are developed for languages with first class primitives for linear communication channels and communication-oriented control flow. In general for GPLs (general purpose programming languages), it is difficult to guarantee the correct implementation of protocol. In this paper, we propose to present an automated verification mechanism to ensure the protocol implementation correctness with respect to a session type specification. To support automatic verification, we design an entailment checking procedure which can handle the verification of a general purpose imperative programming language. Our theory establishes a framework for semantically precise enforcement of protocols, by extending the Separation Logic static analysis technique with a protocol verification mechanism.

关键词： distributed processing formal specification program control structures program diagnostics program verification GPLs automated verification mechanism automatic verification behavior type systems communication-oriented control flow computer software verification distributed programs entailment checking procedure general purpose programming languages imperative programming language linear communication channels protocol implementation correctness protocol specification verification protocol verification mechanism separation logic static analysis technique session type specification Communication channels Computer languages Protocols Safety Software Standards Switches Distributed software Computer programming Languages Communication channels protocols program control structures analysis programme program verification Distributed processing Switches computer software Protocol verification Verification Consumer safety safety Formal specifications

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Building Development Tools Interactively using the EKEKO Meta-programming Library

Building Development Tools Interactively using the EKEKO Met...

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Software Evolution Week / IEEE Conference on Software Maintenance, Reengineering, and Reverse Engineering (CSMR-WCRE)

作者： De Roover, Coen Stevens, Reinout Vrije Univ Brussel Software Languages Lab Brussels Belgium

ISBN: (纸本)9781479937523

EKEKO is a Clojure library for applicative logic meta-programming against an Eclipse workspace. EKEKO has been applied successfully to answering program queries (e.g., "does this bug pattern occur in my code?"), to analyzing project corpora (e.g., "how often does this API usage pattern occur in this corpus?"), and to transforming programs (e.g., "change occurrences of this pattern as follows") in a declarative manner. These applications rely on a seamless embedding of logic queries in applicative expressions. While the former identify source code of interest, the latter associate error markers with, compute statistics about, or rewrite the identified source code snippets. In this paper, we detail the logic and applicative aspects of the EKEKO library. We also highlight key choices in their implementation. In particular, we demonstrate how a causal connection with the Eclipse infrastructure enables building development tools interactively on the Clojure read-eval-print loop.

关键词： application program interfaces logic programming program control structures program debugging query processing software libraries source code (software) API usage pattern Clojure library Clojure read-eval-print loop EKEKO metaprogramming library Eclipse infrastructure Eclipse workspace applicative logic metaprogramming building development tools error markers logic queries program query answering program transformation project corpora analysis source code snippet identification Buildings Computational modeling Java Libraries Logic programming Vectors Visualization

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program understanding using program slivers - An experience report

Program understanding using program slivers - An experience ...

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International Conference on Software Maintenance

作者： Gupta, A Weyerhaeuser Flint River Operations Oglethorpe United States

ISBN: (纸本)081868013X

A large amount of legacy software is written in languages such as FORTRAN and COBOL. Hard-copy and inline documentation for this software is often inadequate to perform maintenance or re-implementation. These tasks are further hampered by legacy structures and programming style such as the use of ''goto''. This paper describes our experience using simple pattern matching tools to obtain ''slivers'' from legacy Process Information Systems. These slivers provided information that assisted in recovering program design. These slivers also helped in identifying segments which could cause problems with two-digit year fields at the turn of the century.

关键词： reverse engineering software maintenance FORTRAN COBOL system documentation software reusability program control structures pattern matching software tools information systems data integrity program understanding program slivers legacy software FORTRAN COBOL hard-copy documentation inline documentation software maintenance software re-implementation programming style goto pattern matching tools legacy process information systems program design recovery two-digit year fields Year 2000 problem

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Run-time Requirement Enforcement for Loop programs on Processor Arrays 18

Run-time Requirement Enforcement for Loop Programs on Proces...

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16th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)

作者： Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781538661956

Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption. To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement: at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives. Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality: 1) architecture-specific reduction by solving for parts of the mapping from the requirements, and 2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied. We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called tightly coupled processor arrays (TCPAs) and demonstrate their effectiveness with a case study. The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy.

关键词： embedded systems Linux multiprocessing systems parallel processing power aware computing program compilers program control structures reconfigurable architectures power aware computing program control structures Runtime Loops compilers Multiprocessing systems Reconfigurable architectures Contraceptive Coil Linux PARALLEL PROCESSING (COMPUTERS) Embedded systems MAPPING(MATHEMATICAL) ARRAY PROCESSORS enforcement

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