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检索条件"主题词=Program Control Structures"
45 条 记 录,以下是11-20 订阅
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Stack-tagged dataflow  26
Stack-tagged dataflow
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26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014
作者: Santiago, Leandro Marzulo, Leandro A.J. Goldstein, Brunno F. Alves, Tiago A.O. França, Felipe M.G. Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil
Dynamic Dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, incremente... 详细信息
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Generalized Hankel Interaction Index Array for control Structure Selection for Discrete-Time MIMO Bilinear Processes and Plants
Generalized Hankel Interaction Index Array for Control Struc...
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IEEE Annual Conference on Decision and control
作者: Hamid Reza Shaker Maryamsadat Tahavori Center for Smart Energy Solutions University of Southern Denmark Odense Denmark
The control technology has been orientated towards decentralized and partially decentralized control strategies. To ensure the success of a decentralized or a partially decentralized control in practice, the first nec... 详细信息
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program analysis too loopy? Set the loops aside
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IET SOFTWARE 2013年 第3期7卷 131-149页
作者: Larson, Eric Seattle Univ Seattle WA 98122 USA
Among the many obstacles to efficient and sound program analysis, loops may be the most prevalent. In program analyses that traverse paths, loops introduce a variable, possibly infinite and number of paths. This study... 详细信息
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Toddler: Detecting Performance Problems via Similar Memory-Access Patterns
Toddler: Detecting Performance Problems via Similar Memory-A...
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35th International Conference on Software Engineering (ICSE)
作者: Nistor, Adrian Song, Linhai Marinov, Darko Lu, Shan Univ Illinois Champaign IL 61820 USA Univ Wisconsin Madison WI 53706 USA
Performance bugs are programming errors that create significant performance degradation. While developers often use automated oracles for detecting functional bugs, detecting performance bugs usually requires time-con... 详细信息
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Quantitative Reasoning for Proving Lock-Freedom  13
Quantitative Reasoning for Proving Lock-Freedom
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28th Annual IEEE/ACM Symposium on Logic in Computer Science (LICS)
作者: Hoffmann, Jan Marmar, Michael Shao, Zhong Yale Univ New Haven CT 06520 USA
This article describes a novel quantitative proof technique for the modular and local verification of lock-freedom. In contrast to proofs based on temporal rely-guarantee requirements, this new quantitative reasoning ... 详细信息
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Path-Sensitive Resource Analysis Compliant with Assertions
Path-Sensitive Resource Analysis Compliant with Assertions
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International Conference on Embedded Software (EMSOFT)
作者: Chu, Duc-Hiep Jaffar, Joxan Natl Univ Singapore Singapore Singapore
We consider the problem of bounding the worst-case resource usage of programs, where assertions about valid program executions may be enforced at selected program points. It is folklore that to be precise, path-sensit... 详细信息
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Automatic Enhanced CDFG Generation based on Runtime Instrumentation
Automatic Enhanced CDFG Generation based on Runtime Instrume...
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IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD)
作者: Yuan, Zhongda Ma, Yuchun Bian, Jinian Zhao, Kang Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China
control and Data Flow Graph (CDFG) is a universal description of program behavior, which is widely used in the co-design of software and hardware. The derivation of CDFG has been done mostly by manually or automatical... 详细信息
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Affine Transformations for Communication and Reconfiguration Optimization of Loops on CGRAs
Affine Transformations for Communication and Reconfiguration...
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IEEE International Symposium on Circuits and Systems (ISCAS)
作者: Liu, Dajiang Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua Univ Res Ctr Mobile Comp Beijing 100084 Peoples R China Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China
A coarse-grained reconfigurable architecture (CGRA) is typically a hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many compute-intensive applications (e.g.,... 详细信息
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Symbolic Parallelization of Loop programs for Massively Parallel Processor Arrays
Symbolic Parallelization of Loop Programs for Massively Para...
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IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
作者: Teich, Juergen Tanase, Alexandru Hannig, Frank Univ Erlangen Nurnberg Dept Comp Sci Nurnberg Germany
In this paper, we present a first solution to the unsolved problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This problem arises for loop programs for which the iter... 详细信息
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Hybrid Relation Calculus
Hybrid Relation Calculus
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18th International Conference on Engineering of Complex Computer Systems (ICECCS)
作者: He, Jifeng E China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China
form only given. Hybrid systems are composed by continuous physical component and discrete control component where the system state evolves over time according to interacting law of discrete and continuous dynamics. C... 详细信息
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