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检索条件"主题词=Program Control Structures"

共 45 条记录，以下是21-30 订阅

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Path-Sensitive Resource Analysis Compliant with Assertions

Path-Sensitive Resource Analysis Compliant with Assertions

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International Conference on Embedded Software (EMSOFT)

作者： Chu, Duc-Hiep Jaffar, Joxan Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781479914432

We consider the problem of bounding the worst-case resource usage of programs, where assertions about valid program executions may be enforced at selected program points. It is folklore that to be precise, path-sensitivity (up to loops) is needed. This entails unrolling loops in the manner of symbolic simulation. To be tractable, however, the treatment of the individual loop iterations must be greedy in the sense once analysis is finished on one iteration, we cannot backtrack to change it. We show that under these conditions, enforcing assertions produces unsound results. The fundamental reason is that complying with assertions requires the analysis to be fully sensitive (also with loops) wrt. the assertion variables. We then present an algorithm where the treatment of each loop is separated in two phases. The first phase uses a greedy strategy in unrolling the loop. This phase explores what is conceptually a symbolic execution tree, which is of enormous size, while eliminates infeasible paths and dominated paths that guaranteed not to contribute to the worst case bound. A compact representation is produced at the end of this phase. Finally, the second phase attacks the remaining problem, to determine the worst-case path in the simplified tree, excluding all paths that violate the assertions from bound calculation. Scalability, in both phases, is achieved via an adaptation of a dynamic programming algorithm.

关键词： dynamic programming iterative methods program control structures program diagnostics trees (mathematics)

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Compiling HPC Kernels for the REDEFINE CGRA 17

Compiling HPC Kernels for the REDEFINE CGRA

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Madhu, Kavitha T. Das, Saptarsi Nalesh, S. Nandy, S. K. Narayan, Ranjani Indian Inst Sci CAD Lab Bangalore Karnataka India Morphing Machines Pvt Ltd Bangalore Karnataka India

ISBN: (纸本)9781479989379

In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communicate through messages. REDEFINE offers the ability to exploit high degree of coarse-grain and pipeline parallelism. The CEs in REDEFINE are enhanced with reconfigurable macro data-paths called HyperCells that enable exploitation of fine-grain and pipeline parallelism at the level of basic instructions in static dataflow order. Application kernels that exhibit regularity in computations and memory accesses such as affine loop nests benefit from the architecture of HyperCell [1], [2]. The proposed compilation flow aims at exposing high degree of parallelism in loop nests in HPC application kernels using polyhedral analysis and generates meta-data to effectively utilize the computational resources in HyperCells. Memory is explicitly managed through compiler's assistance. We address the compilation challenges such as partitioning with load balancing, mapping and scheduling computations and management of operand data while targeting multiple HyperCells in the REDEFINE architecture. The proposed solution scales well meeting the performance objectives of HPC computing.

关键词： data flow computing parallel architectures program compilers program control structures reconfigurable architectures storage management HPC application kernels HPC computing HPC kernels HyperCell architecture REDEFINE CGRA REDEFINE architecture REDEFINE coarse-grain reconfigurable architecture affine loop nests coarse-grain degree compilation flow compiler assistance computational resources compute elements load balancing mapping computation memory accesses memory management operand data management pipeline parallelism polyhedral analysis reconfigurable macro data paths scalable macro-dataflow machine scheduling computation static dataflow order Bandwidth Computer architecture Fabrics Kernel Parallel processing Pipelines Synchronization Architecture CGRA Compiler HPC Loop compilers Store management Coarse-grained Reconfigurable Architecture High Performance Computing program control structures Reconfigurable architectures pipeline Loops Parallel architectures Computer Architecture Load balancing Contraceptive Coil Building construction ARCHITECTURE PARALLEL PROCESSING (COMPUTERS)

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Visualization of Multithreaded Behavior to Facilitate Maintenance of Complex Software Systems

Visualization of Multithreaded Behavior to Facilitate Mainte...

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7th International Conference on the Quality of Information and Communications Technology (QUATIC)

作者： Truemper, Jonas Bohnet, Johannes Voigt, Stefan Doellner, Juergen Univ Potsdam Hasso Plattner Inst Potsdam Germany

ISBN: (纸本)9780769542416

Maintenance accounts for the major part of a software system's total costs. Therein, program comprehension is an important, but complex activity: Typically, up-to-date documentation is not available, so the main reliable source of information on the implementation represent the artifacts of the system's implementation. Understanding software systems is difficult, in particular, if multithreading concepts are involved because state-of-the art development tools provide only limited support for maintenance activities. In addition, concurrency is often not directly reflected by the source code, i.e., there is only a non-obvious correlation between control structures in the source code and a system's runtime behavior. We present a program comprehension technique that helps to analyze and understand runtime behavior of multithreaded software systems and, thereby, facilitates software maintenance tasks. Our approach contains the following concepts: First, light-weight dynamic analysis records executed method calls at runtime. Second, visualization of multithreading trace data allows developers to explore the system behavior post-mortem. The technique forms part of a scalable tool suite for understanding the behavior of complex software systems. We also show how to apply the technique on industrial software systems to solve common maintenance problems.

关键词： complex software system maintenance concurrency concurrency control control structure correlation methods data visualisation dynamic analysis record executed method industrial software system maintenance multi-threading multithreaded software system multithreading parallel computing program comprehension technique program control structures software software maintenance source code state of the art development tool system monitoring system runtime behavior threads visualization

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Evolving programs with Parameters and Loops

Evolving Programs with Parameters and Loops

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2010 IEEE World Congress on Computational Intelligence

作者： Wijesinghe, Gayan Ciesielski, Vic RMIT Univ Sch Comp Sci & Informat Technol Melbourne Vic 3001 Australia

ISBN: (纸本)9781424481262

At the current state of the art, genetic programs do not contain two constructs that commonly occur in programs written by humans, that is, loops and functions with parameters. In this paper we describe an investigation into the evolution of programs for a problem that can only be solved by evolving a parameterised program with one or more loops. We provide training examples of the desired program behaviour for a number of problem sizes and require the evolution of a program P(n) that will give the correct output for any value of n. We have chosen a problem, that of reproducing a binary string to a given number of bits, that can be made harder or easier by adjusting various aspects of the formulation. We are interested seeing in which formulations lead to success and which do not. We conclude that programs with parameters and loops can be successfully evolved if the search space is appropriately restricted by (1) grammars which restrict the possible program structures, (2) limits on program depth and (3) limits on the range of random constants.

关键词： binary string genetic algorithms genetic program grammar grammars parameterised program program behaviour program control structures program evolution program loop program parameter program structure random constant search space

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Exploiting partial operand knowledge

Exploiting partial operand knowledge

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International Conference on Parallel Processing

作者： Mestan, BR Lipasti, MH IBM Corp IBM Microelect Austin TX 78758 USA

ISBN: (纸本)0769520170

Conventional microprocessor designs treat register operands as atomic units. In such designs, no portion of an operand may be consumed until the entire operand has been produced In practice, logic circuits and arithmetic units that generate some portion of an operand in advance of the remaining portions are both feasible and desirable, and have been employed in several existing designs. This paper examines existing and new approaches for exploiting early partial knowledge of an instruction input operands for overlapping the execution of dependent instructions and resolving unknown dependences. In particular we study three applications of partial operand knowledge: disambiguating loads from earlier stores, performing partial tag matching in set-associative caches, and resolving mispredicted conditional branches. We find that each of these is feasible with partial input operands. With the goal of fully exploiting this characteristic, we propose and evaluate a bit-sliced microarchitecture that decomposes a processor data path into 16- and 8-bit slices. We find that a bit-slice design using two 16-bit slices achieves IPC within 1% of an ideal design and attains a 16% speed-up over a conventional pipelined design not using partial operands.

关键词： pipeline processing instruction sets computer architecture program control structures logic circuits microprocessor design register operand instruction input operand dependent instruction partial operand knowledge tag matching set-associative cache conditional branch bit-sliced microarchitecture processor datapath IPC pipelined design

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Recursion Schemes and Logical Reflection

Recursion Schemes and Logical Reflection

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25th Annual IEEE Symposium on Logic in Computer Science (LICS)

作者： Broadbent, Christopher H. Carayol, Arnaud Ong, C-H. Luke Serre, Olivier Univ Oxford Comp Lab Oxford OX1 2JD England Univ Paris Est LIGM CNRS Paris France Univ Paris 07 LIAFA CNRS F-75221 Paris 05 France

ISBN: (纸本)9780769541143

Let R be a class of generators of node-labelled infinite trees, and L be a logical language for describing correctness properties of these trees. Given R is an element of R and phi is an element of L, we say that R-phi is a phi-reflection of R just if (i) R and R. generate the same underlying tree, and (ii) suppose a node u of the tree [[R]] generated by R has label f, then the label of the node u of [[R.]] is (f) under bar if u in [[R]] satisfies phi;it is f otherwise. Thus if [[R]] is the computation tree of a program R, we may regard R-phi as a transform of R that can internally observe its behaviour against a specification phi. We say that R is (constructively) reflective w.r.t. L just if there is an algorithm that transforms a given pair (R, phi) to R-phi. In this paper, we prove that higher-order recursion schemes are reflective w.r.t. both modal mu-calculus and monadic second order (MSO) logic. To obtain this result, we give the first characterisation of the winning regions of parity games over the transition graphs of collapsible pushdown automata (CPDA): they are regular sets defined by a new class of automata. (Order-n recursion schemes are equi-expressive with order-n CPDA for generating trees.) As a corollary, we show that these schemes are closed under the operation of MSO-interpretation followed by tree unfolding a la Caucal.

关键词： Î¼-calculus Collapsible Pushdown Automata Monadic Second Order Logic and Mu-Calculus Global model checking Parity Games Recursion Schemes automata collapsible pushdown automata higher order recursion scheme logical language monadic second order logic program control structures pushdown automata transform transforms tree trees (mathematics)

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Deferring Accelerator Offloading Decisions to Application Runtime

Deferring Accelerator Offloading Decisions to Application Ru...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Vaz, Gavin Riebler, Heinrich Kenter, Tobias Plessl, Christian Univ Paderborn Dept Comp Sci D-33098 Paderborn Germany

ISBN: (纸本)9781479959440

Reconfigurable architectures provide an opportunity to accelerate a wide range of applications, frequently by exploiting data-parallelism, where the same operations are homogeneously executed on a (large) set of data. However, when the sequential code is executed on a host CPU and only data-parallel loops are executed on an FPGA coprocessor, a sufficiently large number of loop iterations (trip counts) is required, such that the control-and data-transfer overheads to the coprocessor can be amortized. However, the trip count of large data-parallel loops is frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code both for the CPU and the coprocessor, and to defer the decision where to execute the appropriate code to the runtime of the application when the trip count of the loop can be determined just at runtime. We demonstrate how an LLVM compiler based toolflow can automatically insert appropriate decision blocks into the application code. Analyzing popular benchmark suites, we show that this kind of runtime decisions is often applicable. The practical feasibility of our approach is demonstrated by a toolflow that automatically identifies loops suitable for vectorization and generates code for the FPGA coprocessor of a Convey HC-1. The toolflow adds decisions based on a comparison of the runtime-computed trip counts to thresholds for specific loops and also includes support to move just the required data to the coprocessor. We evaluate the integrated toolflow with characteristic loops executed on different input data sizes.

关键词： coprocessors field programmable gate arrays program compilers program control structures reconfigurable architectures CPU Convey HC-1 FPGA coprocessor LLVM compiler based toolflow accelerator offloading decision application runtime compile time control-transfer overhead data-parallelism data-transfer overhead decision block large data-parallel loop loop iteration reconfigurable architecture runtime-computed trip count sequential code Benchmark testing Coprocessors Field programmable gate arrays Libraries Memory management Runtime Vectors

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Extraction of Kahn Process Networks from While Loops in Embedded Software 17

Extraction of Kahn Process Networks from While Loops in Embe...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Aguilar, Miguel Angel Eusse, Juan Fernando Leupers, Rainer Ascheid, Gerd Odendahl, Maximilian Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany

ISBN: (纸本)9781479989379

Many embedded applications such as multimedia, signal processing and wireless communications present a streaming processing behavior. In order to take full advantage of modern multi-and many-core embedded platforms, these applications have to be parallelized by describing them in a given parallel Model of Computation (MoC). One of the most prominent MoCs is Kahn Process Network (KPN) as it allows to express multiple forms of parallelism and it is suitable for efficient mapping and scheduling onto parallel embedded platforms. However, describing streaming applications manually in a KPN is a challenging task. Especially, since they spend most of their execution time in loops with unbounded number of iterations. These loops are in several cases implemented as while loops, which are difficult to analyze. In this paper, we present an approach to guide the derivation of KPNs from embedded streaming applications dominated by multiple types of while loops. We evaluate the applicability of our approach on an eight DSP core commercial embedded platform using realistic benchmarks. Results measured on the platform showed that we are able to speedup sequential benchmarks on average by a factor up to 4.3x and in the best case up to 7.7x. Additionally, to evaluate the effectiveness of our approach, we compared it against a state-of-the-art parallelization framework.

关键词： digital signal processing chips embedded systems parallel processing program control structures DSP core embedded platform KPN Kahn process network extraction MoC embedded software embedded streaming applications execution time many-core embedded platforms multicore embedded platforms parallel embedded platforms parallel model-of-computation parallelized applications sequential benchmarks while loops Computational modeling Data mining Long Term Evolution Parallel processing Runtime Switches Uplink DSP Kahn Process Networks MPSoCs Parallelization While Loops PARALLEL PROCESSING (COMPUTERS) Embedded software digital signal processing chips Loops program control structures execution time Long Term Evolution parallelization Runtime up link Digital signal processing Desmoplakin Gene Computational modeling Embedded systems Switches

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Property Directed Invariant Refinement for program Verification

Property Directed Invariant Refinement for Program Verificat...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Welp, Tobias Kuehlmann, Andreas Univ Calif Berkeley Berkeley CA 94720 USA Coverity Inc San Francisco CA USA

ISBN: (纸本)9783981537024

We present a novel, sound, and complete algorithm for deciding safety properties in programs with static memory allocation. The new algorithm extends the program verification paradigm using loop invariants presented in [1] with a counterexample guided abstraction refinement (CEGAR) loop [2] where the refinement is achieved by strengthening loop invariants using the QF_BV generalization of Property Directed Reachability (PDR) discussed in [3, 4]. We compare the algorithm with other approaches to program verification and report experimental results.

关键词： embedded systems program control structures program verification storage allocation QF BV generalization counterexample guided abstraction refinement loop loop invariants program verification paradigm property directed invariant refinement property directed reachability static memory allocation Abstracts Algorithm design and analysis Bismuth Interpolation Resource management Safety Software

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An algorithm of program structure adjustment base on interactive disassembly

An algorithm of program structure adjustment base on interac...

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2011 IEEE 2nd International Conference on Software Engineering and Service Science, ICSESS 2011

作者： Tian, Feng Zhang, Youwei Ma, Dengwei Information Engineering University Zhengzhou Henan Province China

ISBN: (纸本)9781424496969

In the process of program reverse analyzing, anti-track instruction and indirect jump instruction is common to see and difficult to be automatic disassembly analyzed. This article gives a kind of algorithm to adjust program structure, which is based on interactive disassembly, describes theory and detail design of mutual transformation of command section and program section, experiments the average recognition of the algorithm, analyzes and assess the experimental result. © 2011 IEEE.

关键词： Algorithm design and analysis Complexity theory Data mining Flow graphs Interference Process control Software anti-track instruction basic block command section data section data structure data structure data structures describes theory detail design flow chart flow chart flowcharting indirect jump instruction instruction section interactive disassembly program control structures program reverse analyzing process program section program structure adjustment

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