In this brief, we propose an innovative program scheme to mitigatez-direction interference(Z-interference) in charge-trap-based 3-DNANDflash memory. Our approach adjusts the position of trapped electronsin charge trap...
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In this brief, we propose an innovative program scheme to mitigatez-direction interference(Z-interference) in charge-trap-based 3-DNANDflash memory. Our approach adjusts the position of trapped electronsin charge trap nitride (CTN) layer during the program oper-ation by varying the pass voltage (V-pass) on both side wordlines (WLs) of the selected WL. Specifically, cells with a high threshold voltage (V-th) place electrons in the program direction, whereas cells with a low V-th place electrons inthe opposite direction. Depending on the program-verify(PV) level pattern of the aggressor (Agr)-victim cell (Vic),the effective gate pitch can be modified, even though the physical gate pitch is fixed. We validate our proposed scheme using technology computer-aided design (TCAD)simulations and experimental measurements.
A new program scheme using an "eraselike" waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of pre...
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A new program scheme using an "eraselike" waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed programdisturbance, and the V-pass windowcan be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.
The computatiional complexity of several decidable problems about program schemes, recursion schemes, and simple programming languages is considered. The strong equivalence, weak equivalence, containment, halting, and...
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The computatiional complexity of several decidable problems about program schemes, recursion schemes, and simple programming languages is considered. The strong equivalence, weak equivalence, containment, halting, and divergence problems for the single variable program schemes and the linear monadic recursion schemes are shown to be NP-complete. The equivalence problem for the Loop 1 programming language is also shown to be
As the demand of multi-bit/cell NAND flash devices is increasing rapidly, getting a narrow cell Vth distribution becomes more challenging and necessary. To overcome this challenge, an adaptive pulse program (APP) sche...
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ISBN:
(纸本)9781728133201
As the demand of multi-bit/cell NAND flash devices is increasing rapidly, getting a narrow cell Vth distribution becomes more challenging and necessary. To overcome this challenge, an adaptive pulse program (APP) scheme is reported that can tighten the Vth distribution in this work. Compared with conventional incremental step pulse program (ISPP) scheme, this proposed scheme uses adaptive program pulse to the cells with different program speed, which targets to prevent the extension of Vth distribution's upper tail. Our experimental result demonstrates that APP scheme achieves similar to 15% improvement for reducing cell Vth distribution width. This comparison of APP scheme and general ISPP scheme is performed by the FPGA platform using 64-layer 3D charge-trapping NAND flash chip.
Much effort has been performed for performance tuning. However, it is becoming clear that performance tuning is much harder in complicated modern parallel architectures. For performance tuning, compiler approach was p...
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ISBN:
(纸本)9781424452910
Much effort has been performed for performance tuning. However, it is becoming clear that performance tuning is much harder in complicated modern parallel architectures. For performance tuning, compiler approach was prevailing in the era of vector architecture. Today, instead, PSE approach which provides users with abstract programming emerges, which also has a problem in tuning fine points. Another approach is "autotuning" which is a brute force attack for performance tuning. We have proposed that idiom recognition can be a bridge between abstract source programs and concrete architectures. This paper applies term rewriting theory -a very general framework to the idiom recognition system. Moreover, we apply higher order term rewriting to find better patterns. We show that tiling and recursive algorithm scheme patterns can be reinvented by the extended idiom recognition. Furthermore, we discuss a method of enrichment of candidates of optimizations by using the general framework of graph rewriting.
In this note we consider the following decision problems. Let Sigma be a fixed first-order signature. (i) Given a first-order theory or ground theory T over Sigma of Turing degree a, a program scheme p over Sigma, and...
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ISBN:
(纸本)9783642150241
In this note we consider the following decision problems. Let Sigma be a fixed first-order signature. (i) Given a first-order theory or ground theory T over Sigma of Turing degree a, a program scheme p over Sigma, and input values specified by ground terms t(1), ... t(n), does p halt on input t(1), ... t(n), in all models of T? (ii) Given a first-order theory or ground theory T over Sigma of Turing degree a and two program schemes p and q over Sigma, are p and q equivalent in all models of T? When T is empty, these two problems are the classical halting and equivalence problems for program schemes, respectively. We show that problem (i) is Sigma(alpha)(1)-complete and problem (ii) is Pi(alpha)(2)-complete. Both problems remain hard for their respective complexity classes even if Sigma is restricted to contain only a single constant, a single unary function symbol, and a single monadic predicate. It follows from (ii) that there can exist no relatively complete deductive system for scheme equivalence over models of theories of any Turing degree.
In this paper we study the computational power of counters. Two different notions of a counter occur in the literature. One, which we call a two-way counter, is common in automata theory and is provided with the follo...
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In this paper we study the computational power of counters. Two different notions of a counter occur in the literature. One, which we call a two-way counter, is common in automata theory and is provided with the following operations: increment and decrement by 1 and test for zero. Another notion was used in schematology and logics of programs. The corresponding set of operations comes from the simplest algebraic structure of positive integers with increment by 1, reset to 0 and comparison of two counter values. There is no decrementation, therefore we call it a one-way counter. It is known that two two-way counters are enough to simulate a Turing machine. We present the same result for the one-way model: two one-way counters can simulate each Turing machine. We also discuss some consequences of this result for the hierarchy of program schemes. O 1999 Published by Elsevier Science B.V. All rights reserved.
Algebraic models of programs are considered for which the decidability of the equivalence checking problem is proved. A new equivalence checking algorithm stemmed from the well-known Moore technique for finite state a...
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Algebraic models of programs are considered for which the decidability of the equivalence checking problem is proved. A new equivalence checking algorithm stemmed from the well-known Moore technique for finite state automata is introduced. It is shown that, for some subclasses of models, this algorithm is reduced to a polynomial-time equivalence checking procedure.
Inductive program Synthesis or Inductive programming (IP) is the task of generating (recursive) programs from an incomplete specification, such as input/output (I/O) examples. All known IP algorithms can be described ...
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Inductive program Synthesis or Inductive programming (IP) is the task of generating (recursive) programs from an incomplete specification, such as input/output (I/O) examples. All known IP algorithms can be described as search in the space of all candidate programs, with consequently exponential complexity. To constrain the search space and guide the search traditionally program schemes are used, usually given a priori by an expert user. Consequently, all further given data is interpreted w. r. t. this schema which now almost exclusively decides on success and failure, depending on whether it fits the data or not. Instead of trying to fit the data to a given schema indiscriminately, in my thesis (Schema-guided inductive functional programmin through automatic detection of type morphisms, 2010) I proposed to utilise knowledge about data types to choose and fit a suitable schema to the data! Recursion operators associated with data type definitions are well known in functional programming, but less in IP. I showed how to exploit universal properties of type morphisms which may be detected in the given I/O examples. This technique allows to introduce generic recursion schemes, such as catamorphisms or paramorphisms, on arbitrary inductive data types in the analytical inductive functional programming system IGOR II which was already presented here in a previous issue
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