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检索条件"主题词=Program compilers"

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Performance Evaluation of Apache TVM's MetaSchedule for Image Classification Models on Edge Device 13

Performance Evaluation of Apache TVM's MetaSchedule for Imag...

引用

13th IEEE Global Conference on Consumer Electronic, GCCE 2024

作者： Hiramori, Masahiro Oidate, Shingo Mitsubishi Electric Corporation Information Technology R&d Center Kamakura Japan

ISBN: (纸本)9798350355079

Edge deep learning is rapidly being deployed in consumer devices such as home appliances, car navigation systems, and IoT devices. Given these devices' limited computational power and memory, optimizing deep learning models, expressed as tensor programs, is essential. This paper evaluates the inference performance of Apache TVM's MetaSchedule for optimizing image classification models on edge devices. MetaSchedule, a part of the Apache TVM open-source machine learning compiler, automates tensor program optimization for various hardware platforms. Our evaluation of 52 image classification models shows that MetaSchedule outperforms ONNX Runtime in 45 models with up to 4.77x speedup (1.68x on average). However, MetaSchedule lags in models like EfficientNet-v2, VGG, and ResNet50 with larger batch sizes. Future work will focus on expanding model support for MetaSchedule and enhancing optimization performance, contributing to low-latency, privacy-preserving, and bandwidth-efficient inference on edge devices. © 2024 IEEE.

关键词： program compilers

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An Improved Template-Based JIT Compiler for Java 34

An Improved Template-Based JIT Compiler for Java

引用

34th Annual International Conference on Collaborative Advances in Software and Computing, CASCON 2024

作者： Kaur, Harpreet Pirvu, Marius Kent, Kenneth B. University of New Brunswick Faculty of Computer Science FrederictonNB Canada IBM Canada Java JIT Compiler Development TorontoON Canada

ISBN: (纸本)9798331504830

programs that run on a Java virtual machine (JVM)-like Eclipse OpenJ9-are initially interpreted. To improve performance, a Just-in- Time (JIT) compiler may be employed at run time to translate the whole or parts of the program to native code, which can be executed directly instead of being interpreted. In certain environments, where the overhead of an optimizing compiler-the default Testarossa JIT-may be too high to be useful, adding a non-optimizing compiler may prove beneficial to reduce startup times. MicroJIT is such a template-based, lightweight JIT compiler that generates native code with low overhead. This native code runs faster than interpreting the source code, but slower than the optimized code generated by the full JIT compiler. This work proposes improvements to MicroJIT, which include handling polymorphism in a template-based compiler, incorporating exception handling, supporting floating-point types and implementing additional bytecodes. Polymorphism will allow for invocation of virtual methods in Java;exception handling will help maintain the normal desired flow in case of unexpected events;supporting floating-point types will enable compiling methods involving float and double data types;and additional bytecode implementation will increase the bytecode support of MicroJIT. The implementation was tested using the regression framework and evaluated using the DaCapo workloads, most of which depicted increased performance. © 2024 IEEE.

关键词： program compilers

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Dynamic Compiler Optimizations in the Graal VM 17

Dynamic Compiler Optimizations in the Graal VM

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17th IEEE International Scientific Conference on Informatics, INFORMATICS 2024

作者： Mossenbock, Hanspeter Institute for System Software Johannes Kepler University Linz Austria

ISBN: (纸本)9798350387674

Since 2001, our institute is cooperating with Oracle Labs (formerly Sun Labs) on dynamic compiler optimizations and virtual machines. We contributed compiler infrastructure and optimizations both for the Java HotSpot Client compiler and for Oracle's new Graal compiler, which are now used in Oracle's Java environment all over the *** work concentrates on dynamic (just-in-time) compilers that compile an intermediate program representation at run time into highly optimized machine code. In contrast to static compilers (e.g., for C/C++), a dynamic (JIT) compiler imposes new challenges but also offers new optimization opportunities. Both under HotSpot and GraalVM, a program is first executed in interpreted mode, thus guaranteeing fast startup times. During interpretation, run-time profiles about execution frequencies, branch frequencies and observed run-time types are collected. When the execution frequency of a method exceeds a certain threshold, the method is considered "hot"and is passed to the JIT compiler, which compiles it to efficient machine code. Frequently called methods are then executed in machine code while rarely executed methods are interpreted, thus saving compilation time and optimizing the overall *** challenge in JIT compilation is that it happens at run time and must therefore be extremely fast. Elaborate static analysis as well as traditional optimization techniques are often too time-consuming and must therefore be replaced with new and more efficient optimization algorithms. On the other hand, the collected run-time profiles can be leveraged to apply optimizations that are not possible in static compilers. It is even possible to apply "optimistic"optimizations: Usually, optimizations can only be applied when certain preconditions are guaranteed to be true. In our case, however, we can perform optimizations also when we have seen sufficient evidence for the precondition in the profile so far. If the condition turns out to be wrong d

关键词： program compilers

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Defining and Preserving More C Behaviors: Verified Compilation Using a Concrete Memory Model 15

Defining and Preserving More C Behaviors: Verified Compilati...

引用

15th International Conference on Interactive Theorem Proving, ITP 2024

作者： Tolmach, Andrew Chhak, Chris Anderson, Sean Portland State University OR United States

ISBN: (纸本)9783959773379

We propose a concrete ("pointer as integer") memory semantics for C that supports verified compilation to a target environment having simple "public vs. private"data protection based on tagging or sandboxing (such as the WebAssembly virtual machine). Our semantics gives definition to a range of legacy programming idioms that cause undefined behavior in standard C, and are not covered by existing verified compilers, but that often work in practice. Compiler correctness in this context implies that target programs are secure against all control-flow attacks (although not against data-only attacks). To avoid tying our semantics too closely to particular compiler implementation choices, it is parameterized by a novel form of oracle that non-deterministically chooses the addresses of stack and heap allocations. As a proof-of-concept, we formalize a small RTL-like language and verify two-way refinement for a compiler from this language to a low-level machine and runtime system with hardware tagging. Our Coq formalization and proofs are provided as supplementary material. © 2024 Andrew Tolmach, Chris Chhak, and Sean Anderson.

关键词： program compilers

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Automated Control System for Rauvolfia Serpentina Growth Optimization

Automated Control System for Rauvolfia Serpentina Growth Opt...

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2024 IEEE Region 10 Conference, TENCON 2024

作者： Cua, Nathanael Adrian T. Que, Louie T. Soriano, Daniel Iñigo M. Valenciano, Alvin Josh T. Valenzuela, Jana Johannes G. Sim, Matthea Flynne T. Magon, Selverino A. Bandala, Argel A. Vicerra, Ryan Rhay P. Gokongwei College of Engineering De La Salle University Manila Philippines

ISBN: (纸本)9798350350821

The research investigates effective light conditions for the growth of Rauwolfia serpentina, a flower renowned for its medicinal properties. The study meticulously examines the impact of controlling LED grow lights' intensity during both germination and growth phases. To facilitate this investigation, specialized plant nurseries were simulated using the Proteus software and MikroC programming compiler. These nurseries featured black canvas enclosures, PVC pipes, and a PIC16F877A microcontroller equipped with sensors for precise monitoring. By comparing growth outcomes under natural sunlight with those achieved using LED lights with varying exposure durations, the group assessed the plant's efficiency. Notably, the micro controller also controls water pumps, coolers, and a sunroof motor, enhancing environmental control and automation. The controller also features a display used to display the current conditions and status for easier monitoring for the users. The main sensor for the project is the LDR or light dependent resistor which detects how much light is hitting the plants. The findings contribute significantly to the field of controlled environment agriculture, particularly in the context of pharmaceutical plant cultivation. © 2024 IEEE.

关键词： program compilers

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Design of a high-speed two port SRAM compiler based on advanced technology 9

Design of a high-speed two port SRAM compiler based on advan...

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9th International Symposium on Advances in Electrical, Electronics, and Computer Engineering, ISAEECE 2024

作者： Xie, Dongdong Zhang, Lijun Chai, Yongjian School of Rail Transportation Soochow University Suzhou Jiangsu Smart Urban Rail Engineering Research Center China

ISBN: (纸本)9781510683303

This article introduces the design of a high-speed 2-port SRAM compiler based on the 14nm process. In the design process, in order to improve the read and write speed of the circuit, the decoding module was graded for decoding, the storage array was partitioned, and finally, the IO module was redesigned, greatly improving the read and write speed. After the completion of the circuit and layout, post simulation was conducted on the circuit's functions, timing, etc. The simulation voltage was between 0.7 and 1v, the simulation temperature was between -40 and 125 degrees Celsius, and the maximum operating frequency could reach about 2000 MHz, which is about 10% higher than the speed under normal design. © 2024 SPIE.

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REDLC: Learning-driven Reverse Engineering for Deep Learning compilers 35

REDLC: Learning-driven Reverse Engineering for Deep Learning...

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35th IEEE International Symposium on Software Reliability Engineering, ISSRE 2024

作者： Li, Minghui Li, Yang Han, Hao Ke, Xiaopeng Wang, Tongyu Xu, Fengyuan Fang, Liming Nanjing University of Aeronautics and Astronautics Nanjing China Nanjing University Nanjing China

ISBN: (纸本)9798350353884

Deep Learning (DL) compilers such as TVM enable the efficient deployment of diverse DL models on heterogeneous and resource-constrained devices to meet the needs for low latency, privacy protection, and enhanced reliability. However, the booming of on-device DL technology will inevitably attract new types of cybercriminals and industrial spies aiming to steal commercial models. Emerging research focused on model-stealing attacks from the perspective of DL compilers mainly uses heuristic approaches, which do not work well with compiler-optimized models. This work proposes an advanced model-stealing attack pipeline that combines code representation learning and binary analysis to efficiently reverse retrainable DL framework models from TVM-compiled executables. To further improve the accuracy of reversed models, we exploit the computational relationships to correct the prediction of operators in the models using Graph Convolutional Networks. Extensive experiments demonstrate that our approach can recover 18 common DL models with different scales downloaded from Keras repositories with 99% accuracy. © 2024 IEEE.

关键词： program compilers

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An Improved Method for Control Dependency in LLVM 5

An Improved Method for Control Dependency in LLVM

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5th International Conference on Intelligent Computing and Human-Computer Interaction, ICHCI 2024

作者： Li, Jianan Gao, Wei Li, Yingying Han, Lin School of Computer and Artificial Intelligence of ZZU Zhengzhou University Zhengzhou China Zhengzhou University National Supercomputing Center in Zhengzhou Zhengzhou China

ISBN: (纸本)9798350368284

The existence of control dependencies within programs necessitates intricate data reorganization, significantly hindering the vectorization capabilities in automated SIMD compilation processes. The latest iteration of the LLVM compiler, employs a control flow vectorization approach that is contingent upon platform-specific mask intrinsic functions. This reliance results in many loops with IF constructs forfeiting their vectorization potential. To address this, a novel mask instruction transformation technique is introduced, converting IF structures to select instructions. This conversion facilitates control flow vectorization independent of intrinsic functions, effectively transitioning from control to data dependencies. Furthermore, an enhancement to the existing Phi node generation algorithm is proposed to augment control flow vectorization opportunities. Utilizing the TSVC benchmark suite, the experimental results demonstrate a 48% increase in vectorization recognition rate following the implementation of the mask instruction transformation. The maximum speedup ratio achieved is 2.4, with an average speedup ratio of 1.6, outperforming LLVM's current automatic vectorization capabilities. © 2024 IEEE.

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Analyzing SpecFEM-3D's Performance on ARM A64FX Architecture with Compiler Variations 4

Analyzing SpecFEM-3D's Performance on ARM A64FX Architecture...

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4th International Conference on Emerging Trends in Networks and Computer Communications, ETNCC 2024

作者： Jadhav, Om Krishna, Sabbi Vamshi Dinde, Prashant Wandhekar, Sanjay Jat, Dharm Singh HPC-Technologies Group C-DAC Pune India NUST Windhoek Namibia

ISBN: (纸本)9798350353266

This research paper offers a comprehensive performance study of SpecFEM-3D, a well known software package devised for simulating seismic wave propagation in complex 3D geological structures, on the ARM A64FX compute architecture using multiple compilers, including GCC, Arm, and Cray. Then the performance is weighed with the Intel Cascadelake architecture with the native compiler i.e Intel compiler. The purpose of this study is to evaluate the performance and scalability of SpecFEM-3D with diverse compiler setups along with various optimization flags. The methodology incorporates running SpecFEM-3D with different compiler settings and observing the performance with respect to execution time. The results illustrates that, SpecFEM-3D shows scalability on ARM A64FX compute architecture with a single and multinode environment, moreover, demonstrating better performance with the cray compiler. The investigated results gives insights into the performance attributes of SpecFEM-3D on ARM A64FX architectures, aiding informed decision-making for optimizing application performance. © 2024 IEEE.

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Inlined Code Generation for Smalltalk

Inlined Code Generation for Smalltalk

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2024 International Workshop on Smalltalk Technologies, IWST 2024

作者： Franklin, Daniel Mason, Dave Toronto Metropolitan University Toronto Canada

In this paper we present our early work at improving Smalltalk performance by inlining message sends during compilation. Smalltalk developers typically write small method bodies with one or two statements, this limits a compiler's ability to perform many optimizations, e.g. common sub-expression elimination. Inlining messages into a method body produces methods with fewer message sends and more statements allowing the compiler to optimize and generate efficient executable code. There are several challenges to inlining messages in Smalltalk that need to be resolved like detecting cycles in the call graph, resolving methods arguments to their equivalent in the calling method, and handling non-local returns in block arguments. In this paper, we describe the inlining approach taken for the Zag Smalltalk compiler that solves for these issues and improves performance. © 2024 Copyright for this paper by its authors.

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