Use of the Python language in scientific computing has always been characterized by the coexistence of interpreted Python code and compiled native code, written in languages like C or Fortran. This column takes a fres...
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Use of the Python language in scientific computing has always been characterized by the coexistence of interpreted Python code and compiled native code, written in languages like C or Fortran. This column takes a fresh look at the problem and introduces Pythran, a new optimization tool designed to efficiently handle unmodified Python code.
A highly efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing commercial fetch designs are not adaptable and depending on the program behaviour...
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A highly efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing commercial fetch designs are not adaptable and depending on the program behaviour, they can be either insufficient or an overkill. A phase-based adaptive fetch mechanism that can be dynamically adjusted based on feedback information of the program behaviour is introduced. This design adds very little hardware complexity and relegates complex tasks to the software components. It is also very effective: saving 35% and 52% fetch energy on an average compared with a conventional and a trace cache-based fetch unit, respectively. At the same time, performance is improved by 4.7% and 0.8%, respectively.
Testability transformation (TT) is a source-to-source programme transformation that aims to improve the ability of a given test generation method to generate test data for the original programme. Herein, the correctne...
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Testability transformation (TT) is a source-to-source programme transformation that aims to improve the ability of a given test generation method to generate test data for the original programme. Herein, the correctness of testability transformations is shown. Translation validation is the process of proving that the transformed programme is a correct translation of the source programme being compiled. It is widely used to verify the correctness of various compiler optimizations and transformations during scheduling. The value propagation based equivalence checking (VP) method is an efficient translation validation approach proposed to verify the correctness of various compiler optimization applied during scheduling in high-level synthesis. VP-based translation validation of testability transformations is proposed. In particular, it is identified that the existing VP method fails to show the equivalence for some of the TTs. A dynamic cutpoint selection scheme and an enhancement to the VP method to overcome these limitations are shown. The enhanced VP method, called VP_TT, successfully shows the equivalence for the TTs where the VP method fails. Experimental results confirm the usefulness of VP_TT in the verification of testability transformations.
The idea of executing graphical system models is not new. Several accounts of research in this area are well documented. Despite this, such research is still in its infancy, particularly in relation to CASE environmen...
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The idea of executing graphical system models is not new. Several accounts of research in this area are well documented. Despite this, such research is still in its infancy, particularly in relation to CASE environments and the practical application of ideas. The paper considers executability within CASE, with a focus on executable specifications. The importance of executability is highlighted, and some of the work in the field is noted. An experimental executable specification tool is presented. The final conclusions drawn take a look into the envisaged future of executability in CASE.
VLIW machines derive their performance advantage from the parallel execution of independent instructions that have been scheduled by the compiler. The paper evaluates the performance impact of a set of important VLIW ...
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VLIW machines derive their performance advantage from the parallel execution of independent instructions that have been scheduled by the compiler. The paper evaluates the performance impact of a set of important VLIW compilation techniques on non-numerical integer programs. In particular, several key scheduling approaches, including software pipelining versus loop unrolling, DAG-based versus trace-based global scheduling, all-path versus profiled speculation, and restricted versus unrestricted speculative loads, are compared. The evaluation is performed on a uniform VLIW testbed where a relatively fair comparison of these scheduling approaches can be made. The result provides a meaningful insight into the relative benefits of each approach.
A methodology that allows users to efficiently bridge the gap between high-level language and low-level microcode when implementing intensive mathematical operations and manipulations algorithms is discussed. The use ...
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A methodology that allows users to efficiently bridge the gap between high-level language and low-level microcode when implementing intensive mathematical operations and manipulations algorithms is discussed. The use of an optimized special-purpose array processor (SPAP) architecture for numerical computation and a host microprocessor for nonnumerical computation operations is described. The advantages of the optimizing compiler, the target architecture, and the compiler's implementation using AI tools are examined
Aquarius Prolog, a high performance compiler designed and built to test the hypothesis that Prolog can be implemented as efficiently as an imperative language by compiling the more powerful features of logic programmi...
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Aquarius Prolog, a high performance compiler designed and built to test the hypothesis that Prolog can be implemented as efficiently as an imperative language by compiling the more powerful features of logic programming only where they are needed, and then only in the simplest form, is described. The authors begin with some background on logic programming and then discuss the Prolog language in more detail. They present an overview of their compiler, giving its structure and the principles underlying its high performance. They compare their system with two popular high-performance commercial systems and with two implementations of C and conclude with an overview of ways to extend this work
This article traces the history of the programming language SIMULA from the 1950s into the 1970s, focusing in particular on the formative years between 1962 and 1967. It offers no technical appraisal of the language p...
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This article traces the history of the programming language SIMULA from the 1950s into the 1970s, focusing in particular on the formative years between 1962 and 1967. It offers no technical appraisal of the language per se. Rather, it is a sociotechnical analysis aimed at exploring the broader history of the SIMULA project. The article asserts that technological change should be studied in a contextual perspective. Thus the politics surrounding the project and the prehistory of SIMULA are given ample attention.
A computer code serving for an automatic translation of user-written source texts of electrochemical reaction mechanisms into corresponding target texts of mathematical equations that govern the kinetics of electroche...
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A computer code serving for an automatic translation of user-written source texts of electrochemical reaction mechanisms into corresponding target texts of mathematical equations that govern the kinetics of electrochemical systems under transient conditions is reported. The rules of the language enabling symbolic specification of the reaction mechanisms, the compiler options, and conventions regarding the target formulae are outlined and illustrated by examples. A considerable diversity of reaction mechanisms involving equilibrium, non-equilibrium reversible or irreversible reactions that can be electrochemical, heterogeneous non-electrochemical or homogeneous, is permitted. The reactions may involve bulk species (distributed in the electrolyte volume) and interfacial species (localized at the electrodes) of variable or constant concentrations, and electrons. The transient conditions may correspond to a number of electrochemical techniques, including potential-step method, linear potential scan voltammetry and chronopotentiometry. For kinetic problems in one-dimensional space geometry the generated governing equations take the general form of the reaction-advection-diffusion partial differential equations for the concentrations of bulk species (with initial and boundary conditions), optionally coupled with algebraic, ordinary differential or differential-algebraic equations for the concentrations of interfacial species. The governing equations can be obtained in the form of ELSIM problem definitions, enabling further solution by means of this simulation program. Copyright (C) 1996 Elsevier Science Ltd
Manufacturing variability is an increasingly significant problem. Silicon devices that are designed to be identical will display widely ranging characteristics after manufacture. Power use, supported clock frequencies...
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Manufacturing variability is an increasingly significant problem. Silicon devices that are designed to be identical will display widely ranging characteristics after manufacture. Power use, supported clock frequencies and lifespan may all vary considerably. This is of particular concern for embedded systems because of their extensive use of complex system-on-chip (SoC)-based architectures. If this variability is not tolerated by the software, then manufacturing yields are reduced and devices are not used efficiently. This study discusses a novel approach to the integration of variability-mitigation techniques that uses model-driven engineering to explicitly consider variability as part of the development process. Developers can build systems that are much more resilient to variability effects, allowing systems to have higher yields, lower costs and greater reliability. The approach uses code generation and code transformation to simplify design-space exploration and reduce time-to-market. The approach is illustrated with an example of audio processing on a complex multiprocessor SoC with simulated variability, and it is shown to be increasingly effective as system variability becomes more significant.
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