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26th International Conference on Verification Model Checking and Abstract Interpretation

作者： Chait-Roth, Devora Namjoshi, Kedar S. NYU New York NY USA Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (纸本)9783031827020;9783031827037

Smart contracts form the core of Web3 applications. Contracts mediate the transfer of cryptocurrency, making them irresistible targets for hackers. We introduce Asp, a system aimed at easing the construction of provably secure contracts. The Asp system consists of three closely-linked components: a programming language, a defensive compiler, and a proof checker. The language semantics guarantee that Asp contracts are free of commonly exploited vulnerabilities such as arithmetic overflow and reentrancy. The defensive compiler enforces the semantics and translates Asp to Solidity, the most popular contract language. Deductive proofs establish functional correctness and freedom from critical vulnerabilities such as unauthorized access.

关键词： program compilers

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Raccoon: Lightweight Support for Comprehensive Control Flows in Reconfigurable Spatial Architectures

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IEEE Transactions on Parallel and Distributed Systems 2025年第6期36卷 1294-1310页

作者： Kong, Xiangyu Huang, Yi Chen, Longlong Zhu, Jianfeng Li, Liangwei Man, Xingchen Gao, Mingyu Wei, Shaojun Liu, Leibo Tsinghua University School of Integrated Circuits Beijing10084 China Tsinghua University Institute for Interdisciplinary Information Sciences Beijing10084 China

Coarse-grained reconfigurable arrays (CGRAs) have emerged as promising candidates for digital signal processing, biomedical, and automotive applications, where energy efficiency and flexibility are paramount. Yet existing CGRAs suffer from the Amdahl bottleneck caused by constrained control handling via either off-device communication or expensive tag-matching mechanisms. More importantly, mapping control flow onto CGRAs is extremely arduous and time-consuming due to intricate instruction structures and hardware mechanisms. To counteract these limitations, we propose Raccoon, a portable and lightweight framework for CGRAs targeting vast control flows. Raccoon comprises a comprehensive approach that spans microarchitecture, HW/SW interface, and compiler aspects. Regarding microarchitecture, Raccoon incorporates specialized infrastructure for branch- and loop-level control patterns with concise execution mechanisms. The HW/SW interface of Raccoon includes well-characterized abstractions and instruction sets tailored for easy compilation, featuring custom operators and architectural models for control-oriented units. On the compiler front, Raccoon integrates advanced control handling techniques and employs a portable mapper leveraging reinforcement learning and Monte Carlo tree search. This enables agile mapping and optimization of the entire program, ensuring efficient execution and high-quality results. Through the cohesive co-design, Raccoon can empower various CGRAs with robust control-flow handling capabilities, surpassing conventional tagged mechanisms in terms of hardware efficiency and compiler adaptability. Evaluation results show that Raccoon achieves up to a 5.78× improvement in energy efficiency and a 2.24× reduction in cycle count over state-of-the-art CGRAs. Raccoon stands out for its versatility in managing intricate control flows and showcases remarkable portability across diverse CGRA architectures. © 1990-2012 IEEE.

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LLAMA-2 Acceleration Using the ARM Scalable Vector Extension

LLAMA-2 Acceleration Using the ARM Scalable Vector Extensio...

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International Conference on Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2024

作者： Rossi, Federico Cococcioni, Marco Saponara, Sergio Department of Information Engineering University of Pisa Via G. Caruso 16 PI Pisa Italy

ISBN: (纸本)9783031840999

The rise of large language models (LLMs) has spurred recent advances in artificial intelligence (AI), transforming natural language generation and processing. These models perform exceptionally well in a variety of tasks, including machine translation and sentiment analysis, thanks to their unparalleled size and complexity. However, their complexity poses computational difficulties that call for strong hardware acceleration and effective algorithms. To tackle this, we investigate how to speed up LLM processes using the ARM Scalable Vector Extension (SVE). With its ability to vectorize, SVE can potentially improve ARM-based processors’ parallel processing. We present the results of this approach, describing the features of SVE, and going over optimization strategies for LLMs on high-performance computing systems. The results of our experiments show how SVE auto-vectorization enables a speed-up by a factor of up to 4.25× in training time compared to a non-SVE optimized code. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

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Towards Studying the Effect of Compiler Optimizations and Software Randomization on GPU Reliability 16

Towards Studying the Effect of Compiler Optimizations and So...

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16th Workshop on Parallel programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025

作者： López Castillón, Pau Hernández, Xavier Caricchio Kosmidis, Leonidas Spain Spain

ISBN: (纸本)9783959773638

The evolution of Graphics Processing Unit (GPU) compilers has facilitated the support for generalpurpose programming languages across various architectures. The NVIDIA CUDA Compiler (NVCC) employs multiple compilation levels prior to generating machine code, implementing intricate optimizations to enhance performance. These optimizations influence the manner in which software is mapped to the underlying hardware, which can also impact GPU reliability. TASA is a source-to-source code randomization tool designed to alter the mapping of software onto the underlying hardware. It achieves this by generating random permutations of variable and function declarations, thereby introducing random padding between declarations of different types and modifying the program memory layout. Since this modifies their location in the memory, it also modifies their cache placement, affecting both their execution time (due to the different conflicts between them, which result in a different amount of cache misses in every execution), as well as their lifetime in the cache. In this work, which is part of the HiPEAC Student Challenge 2025, we first examine the reproducibility of a subset of data presented in the ACM TACO paper "Assessing the Impact of Compiler Optimizations on GPU Reliability"[10], and second we extend it by combining it with our proposal of software randomization. The paper indicates that the -O3 optimization flag facilitates an increased workload before failures occur within the application. By employing TASA, we investigate the impact of GPU randomization on reliability and performance metrics. By reproducing the results of the paper on a different GPU platform, we observe the same trend as reported in the original publication. Moreover, our preliminary results with the application of software randomization show in several cases an improved Mean Waiting Before Failure (MWBF) compared to the original source code. © Pau López Castillón, Xavier Caricchio Hernández, and Le

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FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis 25

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-...

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33rd ACM/SIGDA International Symposium on Field-programmable Gate Arrays, FPGA 2025

作者： Coulon, Louis Ramirez, Lucas Anderson, Jason Stojilović, Mirjana Ienne, Paolo School of Computer and Communication Sciences EPFL Lausanne Switzerland Electrical and Computer Engineering Department University of Toronto Toronto Canada

ISBN: (纸本)9798400713965

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in contrast, provide ASIC-like performance but limited flexibility, typically supporting only feedforward programs with unambiguous memory accesses, far from the capabilities of HLS compilers. This work introduces a new class of reconfigurable arrays inspired by modern dynamically scheduled HLS (DHLS) tools. Unlike traditional HLS, DHLS compilers no longer produce explicit state machines, eliminating the need for look-up tables. Instead, they delegate scheduling decisions to a set of coarse-grained primitives. Our arrays leverage these primitives as processing elements and combine FPGA-style interconnect topology for high routing flexibility with CGRA-like bus-based interconnect. We present a framework to explore these arrays and evaluate a preliminary architecture using DHLS benchmarks. The results show an average of ∼2× speed improvement, but unfortunately only a ∼20% area reduction compared to an FPGA implemented on the same technology node. © 2025 Copyright held by the owner/author(s).

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Empowering WebAssembly with Thin Kernel Interfaces 25

Empowering WebAssembly with Thin Kernel Interfaces

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20th European Conference on Computer Systems, EuroSys 2025, co-located 30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Ramesh, Arjun Huang, Tianshu Titzer, Ben L. Rowe, Anthony Carnegie Mellon University PittsburghPA United States Carnegie Mellon University Bosch Research PittsburghPA United States

ISBN: (纸本)9798400711961

Wasm is gaining popularity outside the Web as a well-specified low-level binary format with ISA portability, low memory footprint and polyglot targetability, enabling efficient in-process sandboxing of untrusted code. Despite these advantages, Wasm adoption for new domains is often hindered by the lack of many standard system interfaces which precludes reusability of existing software and slows ecosystem growth. This paper proposes thin kernel interfaces for Wasm, which directly expose OS userspace syscalls without breaking intra-process sandboxing, enabling a new class of virtualization with Wasm as a universal binary format. By virtualizing the bottom layer of userspace, kernel interfaces enable effortless application ISA portability, compiler backend reusability, and armor programs with Wasm’s built-in control flow integrity and arbitrary code execution protection. Furthermore, existing capability-based APIs for Wasm, such as WASI, can be implemented as a Wasm module over kernel interfaces, improving reuse, robustness, and portability through better layering. We present an implementation of this concept for two kernels - Linux and Zephyr - by extending a modern Wasm engine and evaluate our system’s performance on a number of sophisticated applications which can run for the first time on Wasm. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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The MLIR Transform Dialect Your Compiler Is More Powerful Than You Think 25

The MLIR Transform Dialect Your Compiler Is More Powerful Th...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Lücke, Martin Paul Zinenko, Oleksandr Moses, William S. Steuwer, Michel Cohen, Albert University of Edinburgh Edinburgh United Kingdom Google DeepMind Paris France University of Illinois Urbana-ChampaignIL United States Google DeepMind CambridgeMA United States Technische Universität Berlin Berlin Germany

ISBN: (纸本)9798400712753

To take full advantage of a specific hardware target, performance engineers need to gain control on compilers in order to leverage their domain knowledge about the program and hardware. Yet, modern compilers are poorly controlled, usually by configuring a sequence of coarse-grained monolithic black-box passes, or by means of predefined compiler annotations/pragmas. These can be effective, but often do not let users precisely optimize their varying compute loads. As a consequence, performance engineers have to resort to implementing custom passes for a specific optimization heuristic, requiring compiler engineering expert knowledge. In this paper, we present a technique that provides fine-grained control of general-purpose compilers by introducing the Transform dialect, a controllable IR-based transformation system implemented in MLIR. The Transform dialect empowers performance engineers to optimize their various compute loads by composing and reusing existing—but currently hidden—compiler features without the need to implement new passes or even rebuilding the compiler. We demonstrate in five case studies that the Transform dialect enables precise, safe composition of compiler transformations and allows for straightforward integration with state-of-the-art search methods. © 2025 Copyright held by the owner/author(s).

关键词： program compilers

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Peephole Optimization Strategies for Intermediate Code in the Compilation Process 1

Peephole Optimization Strategies for Intermediate Code in th...

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1st International Conference on Intelligent Manufacturing and Cloud Computing, ICIMCC 2024

作者： Guan, Yunxin Yun, Jing Sun, Pengfei Su, Xiaoming College of Data Science and Application Inner Mongolia University of Technology Hohhot China

ISBN: (纸本)9781643685779

In the design of modern compilers, the generation and optimization of intermediate code play a crucial role. Serving as a bridge between source code and target machine code, intermediate code provides ample opportunities for optimization. This paper focuses on porthole optimization techniques, proposing a new optimization strategy aimed at reducing unnecessary computations and memory accesses by analyzing control and data flows within intermediate code, thereby enhancing program execution efficiency. We first outline the various stages of the compilation process, followed by a detailed exploration of the basic principles and implementation methods of porthole optimization. Finally, we validate the effectiveness and advantages of this optimization strategy through experiments. The experimental results indicate significant improvements in the execution performance of intermediate code after the adoption of porthole optimization, providing new insights and directions for compiler optimization. © 2025 The Authors.

关键词： program compilers

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LLM-Vectorizer: LLM-Based Verified Loop Vectorizer 25

LLM-Vectorizer: LLM-Based Verified Loop Vectorizer

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Taneja, Jubi Laird, Avery Yan, Cong Musuvathi, Madan Lahiri, Shuvendu K. Microsoft Research Redmond United States University of Toronto Toronto Canada

ISBN: (纸本)9798400712753

Vectorization is a powerful optimization technique that significantly boosts the performance of high performance computing applications operating on large data arrays. Despite decades of research on auto-vectorization, compilers frequently miss opportunities to vectorize code. On the other hand, writing vectorized code manually using compiler intrinsics is still a complex, error-prone task that demands deep knowledge of specific architecture and compilers. In this paper, we evaluate the potential of large-language models (LLMs) to generate vectorized (Single Instruction Multiple Data) code from scalar programs that process individual array elements. We propose a novel finite-state-machine multi-agents based approach that harnesses LLMs and test-based feedback to generate vectorized code. Our findings indicate that LLMs are capable of producing high-performance vectorized code with run-time speedup ranging from 1.1x to 9.4x as compared to the state-of-the-art compilers such as Intel Compiler, GCC, and Clang. To verify the correctness of vectorized code, we use Alive2, a leading bounded translation validation tool for LLVM IR. We describe a few domain-specific techniques to improve the scalability of Alive2 on our benchmark dataset. Overall, our approach is able to verify 38.2% of vectorizations as correct on the TSVC benchmark dataset. © 2025 Copyright held by the owner/author(s).

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Asdf: A Compiler for Qwerty, a Basis-Oriented Quantum programming Language 25

Asdf: A Compiler for Qwerty, a Basis-Oriented Quantum Progra...

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23rd ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2025

作者： Adams, Austin J. Khan, Sharjeel Bhamra, Arjun S. Abusaada, Ryan R. Cabrera, Anthony M. Hoechst, Cameron C. Humble, Travis S. Young, Jeffrey S. Conte, Thomas M. Georgia Institute of Technology AtlantaGA United States Oak Ridge National Laboratory Oak RidgeTN United States

ISBN: (纸本)9798400712753

Qwerty is a high-level quantum programming language built on bases and functions rather than circuits. This new paradigm introduces new challenges in compilation, namely synthesizing circuits from basis translations and automatically specializing adjoint or predicated forms of functions. This paper presents Asdf, an open-source compiler for Qwerty that answers these challenges in compiling basis-oriented languages. Enabled with a novel high-level quantum IR implemented in the MLIR framework, our compiler produces OpenQASM 3 or QIR for either simulation or execution on hardware. Our compiler is evaluated by comparing the fault-tolerant resource requirements of generated circuits with other compilers, finding that Asdf produces circuits with comparable cost to prior circuit-oriented compilers. © 2025 Copyright held by the owner/author(s).

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