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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Arranz Olmos, Santiago Barthe, Gilles Chuengsatiansup, Chitchanok Gregoire, Benjamin Laporte, Vincent Oliveira, Tiago Schwabe, Peter Yarom, Yuval Zhang, Zhiyuan MPI-SP Bochum Germany Imdea Software Institute Madrid Spain University of Melbourne Melbourne Australia Inria Sophia Antipolis France Université de Lorraine Cnrs Inria Loria Nancy France Sandbox Aq Palo AltoCA United States Radboud University Nijmegen Netherlands Ruhr University Bochum Bochum Germany

ISBN: (纸本)9798400710797

Spectre attacks void the guarantees of constant-time cryptographic code by leaking secrets during speculative execution. Recent research shows that such code can be protected from Spectre-v1 attacks with minimal overhead, but leaves open the question of protecting against other Spectre variants. In this work, we design, validate, implement, and verify a new approach to protect cryptographic code against all known classes of Spectre attacks, in particular Spectre-RSB. Our approach combines a new value-dependent information-flow type system that ensures that no secrets leak even under speculative execution and a compiler transformation that enables it on the generated low-level code. We first prove the soundness of the type system and the correctness of the compiler transformation using the Coq proof assistant. We then implement our approach in the Jasmin framework for high-assurance cryptography and demonstrate that the overhead incurred by all Spectre protections is below 2% for most cryptographic primitives and reaches only about 5 - 7% for the more complex post-quantum key-encapsulationkmechanism Kyber. © 2025 ACM.

关键词： program compilers

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FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications 31

FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully...

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31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025

作者： Park, Yongmo Amarnath, Aporva Pal, Subhankar Swaminathan, Karthik Buyuktosunoglu, Alper Shaul, Hayim Aharoni, Ehud Drucker, Nir Lu, Wei D. Soceanu, Omri Bose, Pradip IBM T. J. Watson Research Center NY United States IBM Research Israel University of Michigan MI United States

ISBN: (纸本)9798331506476

Fully homomorphic encryption (FHE) is a powerful cryptographic technique that enables computation on encrypted data without needing to decrypt it. It has broad applications in scenarios where sensitive data needs to be processed in the cloud or in other untrusted environments. FHE applications are both compute- and memory-intensive, owing to expensive operations on large data. While prior works address the challenges of efficient compute using dedicated hardware, expensive memory transfers still remain a major limiting factor. In this work, we propose a hierarchical near-DRAM processing (NDP) solution for FHE applications, called FHENDI, that harnesses the massive DRAM bank bandwidth. We observe various data access patterns in FHE that reveal distinct levels of parallelism: element-wise, limb-wise, coefficient-wise, and ciphertext-wise. FHENDI exploits these levels of parallelism to map FHE operations and data onto different hierarchies of our design, while addressing three major challenges with NDP for FHE: (i) the lack of bank-to-bank communication support, (ii) limited die-to-die bandwidth, and (iii) large memory access latencies. We resolve the first problem through a novel, conflict-free mapping algorithm built atop localized permutation networks that enables efficient element-wise and butterfly operations in FHE. The second problem is addressed by pipelining the execution of parallel bootstrap operations observed in compiled FHE workloads. Finally, we hide the memory access latency behind computation latency by exploiting a dual-banking scheme and subarray-level parallelism (SLP) of the DRAM banks. We evaluate FHENDI using representative workloads in the domains of privacy-preserving machine learning inference on CNNs and Transformers, database range query, and sorting, that are obtained using a compiler framework called HElayers. We compare FHENDI with a server-class CPU and GPU running the state-of-the-art HEaaN library, and an FHE accelerator ASIC, and repo

关键词： program compilers

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Compiler Support for Semi-manual AoS-to-SoA Conversions with Data Views 15th

Compiler Support for Semi-manual AoS-to-SoA Conversions wit...

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15th International Conference on Parallel Processing and Applied Mathematics, PPAM 2024

作者： Radtke, Pawel K. Weinzierl, Tobias Department of Computer Science Durham University Durham United Kingdom

ISBN: (纸本)9783031856969

The C programming language and its cousins such as C++ stipulate the static storage of sets of structured data: Developers have to commit to one, invariant data model—typically a structure-of-arrays (SoA) or an array-of-structs (AoS)—unless they manually rearrange, i.e. convert it throughout the computation. Whether AoS or SoA is favourable depends on the execution context and algorithm step. We propose a language extension based upon C++ attributes through which developers can guide the compiler what memory arrangements are to be used. The compiler can then automatically convert (parts of) the data into the format of choice prior to a calculation and convert results back afterwards. As all conversions are merely annotations, it is straightforward for the developer to experiment with different storage formats and to pick subsets of data that are subject to memory rearrangements. Our work implements the annotations within Clang and demonstrates their potential impact through a smoothed particle hydrodynamics (SPH) code. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： program compilers

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Exo 2: Growing a Scheduling Language 25

Exo 2: Growing a Scheduling Language

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Ikarashi, Yuka Qian, Kevin Droubi, Samir Reinking, Alex Bernstein, Gilbert Louis Ragan-Kelley, Jonathan Mit Csail CambridgeMA United States Adobe CambridgeMA United States University of Washington SeattleWA United States

ISBN: (纸本)9798400706981

User-schedulable languages (USLs) help programmers productively optimize programs by providing safe means of transforming them. Current USLs are designed to give programmers exactly the control they want, while automating all other concerns. However, there is no universal answer for what performance-conscious programmers want to control, how they want to control it, and what they want to automate, even in relatively narrow domains. We claim that USLs should, instead, be designed to grow. We present Exo 2, a scheduling language that enables users to define new scheduling operations externally to the compiler. By composing a set of trusted, fine-grained primitives, users can safely write their own scheduling library to build up desired automation. We identify actions (ways of modifying code), inspection (ways of interrogating code), and references (ways of pointing to code) as essential for any user-extensible USL. We fuse these ideas into a new mechanism called Cursors that enables the creation of scheduling libraries in user code. We demonstrate libraries that amortize scheduling effort across more than 80 high-performance kernels, reducing total scheduling code by an order of magnitude and delivering performance competitive with state-of-the-art implementations on three different platforms. © 2025 ACM.

关键词： program compilers

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HALO: Loop-aware Bootstrapping Management for Fully Homomorphic Encryption 25

HALO: Loop-aware Bootstrapping Management for Fully Homomorp...

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Cheon, Seonyoung Lee, Yongwoo Youm, Hoyun Kim, Dongkwan Yun, Sungwoo Jeong, Kunmo Lee, Dongyoon Kim, Hanjun Yonsei University Seoul Korea Republic of Stony Brook University Stony Brook United States

ISBN: (纸本)9798400706981

Thanks to the computation ability on encrypted data, fully homomorphic encryption (FHE) is an attractive solution for privacy-preserving computation. Despite its advantages, FHE suffers from limited applicability in small programs because repeated FHE multiplications deplete the level of a ciphertext, which is finite. Bootstrapping reinitializes the level, thus allowing support for larger programs. However, its high computational overhead and the risk of level underflow require sophisticated bootstrapping placement, thereby increasing the programming burden. Although a recently proposed compiler automatizes the bootstrapping placement, its applicability is still limited due to lack of loop support. This work proposes the first loop-aware bootstrapping management compiler, called HALO, which optimizes bootstrapping placement in an FHE program with a loop. To correctly support bootstrapping-enabled loops, HALO matches encryption types and levels between live-in and loop-carried ciphertexts in the loops. To reduce the bootstrapping overheads, HALO decreases the number of bootstrapping within a loop body by packing the loop-carried variables to a single ciphertext, reduces wasted levels in a short loop body by unrolling the loop, and optimizes the bootstrapping latency by adjusting the target level of bootstrapping as needed. For seven machine learning programs with flat and nested loops, HALO shows 27% performance speedup compared to the state-of-the-art compiler that places bootstrapping operations on fully unrolled loops. In addition, HALO reduces the compilation time and code size by geometric means of 209.12x and 11.0x compared to the compiler, respectively. © 2025 ACM.

关键词： program compilers

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Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning 25

Enhancing CGRA Efficiency Through Aligned Compute and Commun...

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Li, Zhaoying Dangi, Pranav Yin, Chenyang Bandara, Thilini Kaushalya Juneja, Rohan Tan, Cheng Bai, Zhenyu Mitra, Tulika National University of Singapore Singapore Singapore Peking University Beijing China Google San Francisco United States

ISBN: (纸本)9798400706981

Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called motifs. The primary contribution is the identification of these structural motifs within the dataflow graphs and the development of an efficient collective execution and routing strategy tailored to these motifs. The Plaid architecture employs a novel collective processing unit that can execute multiple operations of a motif and route related data dependencies together. The Plaid compiler can hierarchically map the dataflow graph and judiciously schedule the motifs. Our design achieves a 43% reduction in power consumption and 46% area savings compared to the baseline high-performance spatio-temporal CGRA, all while preserving its generality and performance levels. In comparison to the baseline energy-efficient spatial CGRA, Plaid offers a 1.4× performance improvement and a 48% area savings, with almost the same power. © 2025 ACM.

关键词： program compilers

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Cinnamon: A Framework for Scale-Out Encrypted AI 25

Cinnamon: A Framework for Scale-Out Encrypted AI

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Jayashankar, Siddharth Chen, Edward Tang, Tom Zheng, Wenting Skarlatos, Dimitrios Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9798400706981

Fully homomorphic encryption (FHE) is a promising cryptographic solution that enables computation on encrypted data, but its adoption remains a challenge due to steep performance overheads. Although recent FHE architectures have made valiant efforts to narrow the performance gap, they not only have massive monolithic chip designs but also only target small ML workloads. We present Cinnamon, a framework for accelerating state-of-the-art ML workloads that are encrypted using FHE. Cinnamon accelerates encrypted computing by exploiting parallelism at all levels of a program, using novel algorithms, compilers, and hardware techniques to create a scale-out design for FHE as opposed to a monolithic chip design. Our evaluation of the Cinnamon framework on small programs shows a 2.3× improvement in performance compared to prior state-of-the-art designs. Further, we use Cinnamon to show for the first time the scalability of large ML models such as the BERT language model in FHE. Cinnamon achieves a speedup of 36,600× compared to a CPU bringing down the inference time from 17 hours to 1.67 seconds thereby enabling new opportunities for privacy-preserving machine learning. Finally, Cinnamon's parallelization strategies and architectural extensions reduce the required resources per-chip leading to a 5× and 2.68× improvement in performance-per-dollar compared to state-of-the-art monolithic and chiplet architectures respectively. © 2025 ACM.

关键词： program compilers

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Target-Aware Implementation of Real Expressions 25

Target-Aware Implementation of Real Expressions

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30th ACM International Conference on Architectural Support for programming Languages and Operating Systems, ASPLOS 2025

作者： Saiki, Brett Brough, Jackson Regehr, Jonas Ponce, Jesus Pradeep, Varun Akhileshwaran, Aditya Tatlock, Zachary Panchekha, Pavel University of Washington SeattleWA United States University of Utah Salt Lake CityUT United States

ISBN: (纸本)9798400706981

New low-precision accelerators, vector instruction sets, and library functions make maximizing accuracy and performance of numerical code increasingly challenging. Two lines of work - -traditional compilers and numerical compilers - -attack this problem from opposite directions. Traditional compiler backends optimize for specific target environments but are limited in their ability to balance performance and accuracy. Numerical compilers trade off accuracy and performance, or even improve both, but ignore the target environment. We join aspects of both to produce Chassis, a target-aware numerical compiler. Chassis compiles mathematical expressions to operators from a target description, which lists the real expressions each operator approximates and estimates its cost and accuracy. Chassis then uses an iterative improvement loop to optimize for speed and accuracy. Specifically, a new instruction selection modulo equivalence algorithm efficiently searches for faster target-specific programs, while a new cost-opportunity heuristic supports iterative improvement. We demonstrate Chassis capabilities on 9 different targets, including hardware ISAs, math libraries, and programming languages. Chassis finds better accuracy and performance trade-offs than both Clang (by 3.5×) or Herbie (by up to 2.0×) by leveraging low-precision accelerators, accuracy-optimized numerical helper functions, and library subcomponents. © 2025 ACM.

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MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Hamdi, Mohamed Amine Daghero, Francesco Sarda, Giuseppe Maria Delm, Josse Van Symons, Arne Benini, Luca Verhelst, Marian Pagliari, Daniele Jahier Burrello, Alessio Politecnico di Torino Italy KU Leuven Belgium IMEC Belgium University of Bologna Italy

Streamlining the deployment of Deep Neural Networks (DNNs) on heterogeneous edge platforms, coupling within the same micro-controller unit (MCU) instruction processors and hardware accelerators for tensor computations, is becoming one of the crucial challenges of the TinyML field. The best-performing DNN compilation toolchains are usually deeply customized for a single MCU family, and porting them to a different one implies labor-intensive re-development of almost the entire compiler. On the opposite side, retargetable toolchains, such as TVM, fail to exploit the capabilities of custom accelerators, producing general but unoptimized code. To overcome this duality, we introduce MATCH, a novel TVM-based DNN deployment framework designed for easy agile retargeting across different MCU processors and accelerators, thanks to a customizable model-based hardware abstraction. We show that a general and retargetable mapping framework can compete with, and even outperform custom toolchains on diverse targets while only needing the definition of an abstract hardware cost model and a SoC-specific API. We tested MATCH on two state-of-the-art heterogeneous MCUs, GAP9 and DIANA. On the four DNN models of the MLPerf Tiny suite MATCH reduces inference latency on average by 60.87× on DIANA, compared to using the plain TVM, thanks to the exploitation of the on-board HW accelerator. Compared to HTVM, a fully customized toolchain for DIANA, we still reduce the latency by 16.94%. On GAP9, using the same benchmarks, we improve the latency by 2.15× compared to the dedicated DORY compiler, thanks to our heterogeneous DNN mapping approach that synergically exploits the DNN accelerator and the eight-cores cluster available on board. © 1982-2012 IEEE.

关键词： program compilers

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Importance of C/C++ compiler choice for performance and energy consumption of multithreaded WZ factorization

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Bulletin of the Polish Academy of Sciences: Technical Sciences 2025年第2期73卷

作者： Bylina, Beata Piekarz, Monika Bylina, Jaroslaw Maria Curie-Sklodowska University Pl. M. Curie-Sklodowskiej 5 Lublin20-031 Poland

The choice of C/C++ compiler significantly impacts the performance and energy consumption of multithreaded numerical algorithms related to linear algebra. This study investigates the effects of the C/C++ compiler choice and processor frequency scaling (using dynamic voltage frequency scaling) on the performance and energy consumption of the multithreaded WZ factorization on three different computing platforms, two featuring Intel Xeon processors and one featuring AMD EPYC processor. The factorization is implemented both without optimization techniques and with strip-mining. Based on time and energy tests, we have demonstrated that, for the WZ factorization (in both implementations), each compiler reacts somewhat differently to frequency changes, thus affecting overall performance and energy consumption. The Intel compilers achieved the best performance and energy savings in a multithreaded environment compared to the other compilers on each of the tested computing platforms. © 2025 The Author(s).

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