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Micro execution 2014

Micro Execution

引用

36th International Conference on Software Engineering (ICSE)

作者： Godefroid, Patrice Microsoft Res One Microsoft Way Redmond WA 98052 USA

ISBN: (纸本)9781450327565

Micro execution is the ability to execute any code fragment without a user-provided test driver or input data. The user simply identifies a function or code location in an exe or dll. A runtime Virtual Machine (VM) customized for testing purposes then starts executing the code at that location, catches all memory operations before they occur, allocates memory on-the-fly in order to perform those read/write memory operations, and provides input values according to a customizable memory policy, which defines what read memory accesses should be treated as inputs. MicroX is a first prototype VM allowing micro execution of x86 binary code. No test driver, no input data, no source code, no debug symbols are required: MicroX automatically discovers dynamically the Input/Output interface of the code being run. Input values are provided as needed along the execution and can be generated in various ways, e.g., randomly or using some other test-generation tool. To our knowledge, MicroX is the first VM designed for test isolation and generation purposes. This paper introduces micro execution and discusses how to implement it, strengths and limitations, applications, related work and long-term goals.

关键词： program execution Testing Virtual Machine

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On Energy Efficiency of Reconfigurable Systems with Run-Time Partial Reconfiguration

On Energy Efficiency of Reconfigurable Systems with Run-Time...

引用

21st IEEE International Conference on Application-Specific Systems, Architectures and Processors

作者： Liu, Shaoshan Pittman, Richard Neil Forin, Alessandro Gaudiot, Jean-Luc Univ Calif Irvine EECS Irvine CA 92717 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781424469673

In this paper we study whether partial reconfiguration can be used to reduce FPGA energy consumption. In an ideal scenario, we will have a hardware accelerator to assist with certain parts of program execution. When the accelerator is not active, we use partial reconfiguration to unload it to reduce both static and dynamic power. However, the reconfiguration process may introduce a high energy overhead, thus it is unclear whether this approach is feasible. To approach this problem, we identify the conditions under which partial reconfiguration can be used to reduce energy consumption, and we propose solutions to minimize the configuration energy overhead. The results of our study show that by using partial reconfiguration to reduce the power consumption of the accelerator when it is inactive, we can accelerate program execution and at the same time halve the overall energy consumption.

关键词： Reconfiguration Power consumption energy consumption Energy efficiency hardware accelerator UNLOADING program execution Runtime Partial Accelerators

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Dynamic Detection and Mitigation of DMA Races in MPSoCs 18

Dynamic Detection and Mitigation of DMA Races in MPSoCs

引用

18th Euromicro Conference on Digital System Design (DSD)

作者： Saidi, Selma Falcone, Ylics Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Network Engn Braunschweig Germany Univ Grenoble Alpes Inria LIG F-38000 Grenoble France

ISBN: (纸本)9781467380355

Explicitly managed memories have emerged as a good alternative for multicore processors design in order to reduce energy and performance costs. Memory transfers then rely on Direct Memory Access (DMA) engines which provide a hardware support for accelerating data. However, programming explicit data transfers is very challenging for developers who must manually orchestrate data movements through the memory hierarchy. This is in practice very error-prone and can easily lead to memory inconsistency. In this paper, we propose a runtime approach for monitoring DMA races. The monitor acts as a safeguard for programmers and is able to enforce at runtime a correct behavior w.r.t the semantics of the program execution. We validate the approach using traces extracted from industrial benchmarks and executed on the multiprocessor system-on-chip platform STHORM. Our experiments demonstrate that the monitoring algorithm has a low overhead (less than 1.5 KB) of on-chip memory consumption and an overhead of less than 2% of additional execution time.

关键词： DIAGNOSIS OF MULTIPLE ALARMS SYSTEM DYNAMIC MECHANICAL ANALYSIS memory hierarchy Memory multiprocessor system on chip data transmission program execution Memory Racial Stocks Multi-core processors enforcement Safeguards Computer personnel execution time Developers

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A PCM Translation Layer for Integrated Memory and Storage Management 14

A PCM Translation Layer for Integrated Memory and Storage Ma...

引用

International Conference on Hardware / Software Codesign and System Synthesis (CODES+ISSS)

作者： Chang, Bing-Jing Chang, Yuan-Hao Chang, Hung-Sheng Kuo, Tei-Wei Li, Hsiang-Pang Macronix Int Co Ltd Emerging Syst Lab Hsinchu Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781450330510

Phase change memory (PCM) is known for its potentials as main memory and as storage. In contrast to the past work, this work presents a PCM translation layer that considers how the main memory is used by the operating system together with the usage patterns of storage by trading their performance and reliability. In particular, a joint management scheme is proposed to improve the capability of PCM as both main memory and storage so as to enhance the performance of the entire system. The endurance issue of PCM for main memory is resolved by utilizing the potentially large capacity of the PCM storage space with limited modifications to the existing operating system implementations. Moreover, three commands are proposed to help operating system engineers to take advantage of PCM as main memory and storage by reducing I/O overheads and speeding up both the initialization and termination of program executions. The experimental results show that the performance of PCM as both main memory and storage can be significantly improved with reasonable lifetime, while the system overhead is very limited under coarse-grained wear leveling.

关键词： operating systems (computers) phase change memories program verification storage management I/O overheads PCM storage space PCM translation layer coarse-grained wear leveling integrated memory management integrated storage management joint management scheme operating system operating system implementations phase change memory program executions Hardware Joints Memory management Operating systems Performance evaluation Phase change materials Random access memory Store management Operating systems Phase change memory main memory Pulse code modulation program execution random access machine program verification Phase change materials Computer hardware Joints Joints Performance Evaluation

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HeapTherapy: An Efficient End-to-end Solution against Heap Buffer Overflows 45

HeapTherapy: An Efficient End-to-end Solution against Heap B...

引用

45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

作者： Zeng, Qiang Zhao, Mingyi Liu, Peng Penn State Univ University Pk PA 16802 USA

ISBN: (纸本)9781479986293

For decades buffer overflows have been one of the most prevalent and dangerous software vulnerabilities. Although many techniques have been proposed to address the problem, they mostly introduce a very high overhead while others assume the availability of a separate system to pinpoint attacks or provide detailed traces for defense generation, which is very slow in itself and requires considerable extra resources. We propose an efficient solution against heap buffer overflows that integrates exploit detection, defense generation, and overflow prevention in a single system, named HeapTherapy. During program execution it conducts on-the-fly lightweight trace collection and exploit detection, and initiates automated diagnosis upon detection to generate defenses in realtime. It can handle both over-write and over-read attacks, such as the recent Heartbleed attack. The system has no false positives, and keeps effective under polymorphic exploits. It is compliant with mainstream hardware and operating systems, and does not rely on specific allocation algorithms. We evaluated HeapTherapy on a variety of services (database, web, and ftp) and benchmarks (SPEC CPU2006);it incurs a very low average overhead in terms of both speed (6.2%) and memory (7.7%).

关键词： Buffer overflows heap automatic diagnosis split system file transfer protocol Operating systems defenses False-positives Allocation Algorithm program execution

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Data Remanence and Digital Forensic Investigation for CUDA Graphics Processing Units 14

Data Remanence and Digital Forensic Investigation for CUDA G...

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IFIP/IEEE International Symposium on Integrated Network Management (IM)

作者： Bellekens, Xavier Paul, Greig Irvine, James M. Tachtatzis, Christos Atkinson, Robert C. Kirkham, Tony Renfrew, Craig Univ Strathclyde Glasgow G1 1XQ Lanark Scotland Keysight Technol Santa Rosa CA USA

ISBN: (纸本)9783901882760

This paper investigates the practicality of memory attacks on commercial Graphics Processing Units (GPUs). With recent advances in the performance and viability of using GPUs for various highly-parallelised data processing tasks, a number of security challenges are raised. Unscrupulous software running subsequently on the same GPU, either by the same user, or another user, in a multi-user system, may be able to gain access to the contents of the GPU memory. This contains data from previous program executions. In certain use-cases, where the GPU is used to offload intensive parallel processing such as pattern matching for an intrusion detection system, financial systems, or cryptographic algorithms, it may be possible for the GPU memory to contain privileged data, which would ordinarily be inaccessible to an unprivileged application running on the host computer. With GPUs potentially yielding access to confidential information, existing research in the field is built upon, to investigate the practicality of extracting data from global, shared and texture memory, and retrieving this data for further analysis. These techniques are also implemented on various GPUs using three different Nvidia CUDA versions. A novel methodology for digital forensic examination of GPU memory for remanent data is then proposed, along with some suggestions and considerations towards countermeasures and anti-forensic techniques.

关键词： Graphics Processing Unit GRAPPER PICK UP Memory Memory on line data service program execution extracting data INTRUSION DETECTION SYSTEMS remanent magnetization Access Pattern matching PARALLEL PROCESSING (COMPUTERS)

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Applying perceptrons to computer architecture

Applying perceptrons to computer architecture

引用

International Conference on Intelligent Sensing and Information Processing

作者： Black, M Franklin, M Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

ISBN: (纸本)0780388402

Speculation plays,in ever-increasing role it optimising the execution of programs in computer architecture. Speculative decision-makers are typically required to have high speed and small size, thus limiting their complexity, and capability. Because of these restrictions, decision-makers often consider only a fixed subset of the available data in making decisions, and consequently do not realize their potential accuracy. Perceptrons, or simple neural networks, could be highly useful in speculation as a means of examining a larger quantity of available data, and identfying which data lead to accurate results. Recent research has demonstrated that perceptrons can operate successfully within the narrow restrictions of speculation in computer architecture. In this paper, we examine two successful applications of perceptrons to speculation problems: branch prediction and confidence estimation. We analyse the limitations of perceptrons in these two applications, and use them to discuss how perceptrons could be applied in future computer architecture applications. Finally, we present three promising new applications of perceptrons in computer architecture.

关键词： decision making multilayer perceptrons parallel architectures program compilers branch prediction computer architecture confidence estimation neural networks perceptrons program execution speculative decision-makers Neural Networks (Computer) Computer Architecture Branch-prediction compilers Multilayer perceptrons Parallel architectures program execution Neural network

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gem5-Approxilyzer: An Open-Source Tool for Application-Level Soft Error Analysis 49

gem5-Approxilyzer: An Open-Source Tool for Application-Level...

引用

49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

作者： Venkatagiri, Radha Ahmed, Khalique Mahmoud, Abdulrahman Misailovic, Sasa Marinov, Darko Fletcher, Christopher W. Adve, Santa, V Univ Illinois Champaign IL 61820 USA

ISBN: (纸本)9781728100562

Modern systems are increasingly susceptible to soft errors in the field and traditional redundancy-based mitigation techniques are too expensive to protect against all errors. Recent techniques, such as approximate computing and various low-cost resilience mechanisms, intelligently trade off inaccuracy in program output for better energy, performance, and resiliency overhead. A fundamental requirement for realizing the full potential of these techniques is a thorough understanding of how applications react to errors. Approxilyzer is a state-of-the-art tool that enables an accurate, efficient, and comprehensive analysis of how errors in almost all dynamic instructions in a program's execution affect the quality of the final program output. While useful, its adoption is limited by its implementation using the proprietary Simics infrastructure and the SPARC ISA. We present gem5-Approxilyzer, a re-implementation of Approxilyzer using the open-source gem5 simulator. gem5-Approxilyzer can be extended to different ISAs, starting with x86 in this work. We show that gem5-Approxilyzer is both efficient (up to two orders of magnitude reduction in error injections over a naive campaign) and accurate (average 92% for our experiments) in predicting the program's output quality in the presence of errors. We also compare the error profiles of five workloads under x86 and SPARC to further motivate the need for a tool like gem5-Approxilyzer.

关键词： Tools Degradation Resilience Error analysis Approximate computing Performance analysis Registers Error analysis Registers program output Resilience Osteonectin scalable processor architecture open source Energy performance program execution deterioration

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HW/SW Co-Detection of Transient and Permanent Faults with Fast Recovery in Statically Scheduled Data Paths

HW/SW Co-Detection of Transient and Permanent Faults with Fa...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Schoelzel, Mario Brandenburg Tech Univ Cottbus Dept Comp Sci Cottbus Germany

ISBN: (纸本)9783981080162

This paper describes a hardware-/software-based technique to make the data path of a statically scheduled super scalar processor fault tolerant. The results of concurrently executed operations can be compared with little hardware overhead in order to detect a transient or permanent fault. Furthermore, the hardware extension allows to recover from a fault within one to two clock cycles and to distinguish between transient and permanent faults. If a permanent fault was detected, this fault is masked for the rest of the program execution such that no further time is needed for recovering from that fault. The proposed extensions were implemented in the data path of a simple VLIW processor in order to prove the feasibility and to determine the hardware overhead. Finally a reliability analysis is presented. It shows that for medium and large scaled data paths our extension provides an up to 98% better reliability than triple modular redundancy.

关键词： permanent fault channels (data transmission) clock cycle program execution Computer hardware Paths Reliability analysis

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A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events 47

A Practical Methodology for Measuring the Side-Channel Signa...

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47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Callan, Robert Zajic, Alenka Prvulovic, Milos Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781479969982

This paper presents a new metric, which we call Signal Available to Attacker (SAVAT), that measures the side channel signal created by a specific single-instruction difference in program execution, i.e. the amount of signal made available to a potential attacker who wishes to decide whether the program has executed instruction/event A or instruction/event B. We also devise a practical methodology for measuring SAVAT in real systems using only user-level access permissions and common measurement equipment. Finally, we perform a case study where we measure electromagnetic (EM) emanations SAVAT among 11 different instructions for three different laptop systems. Our findings from these experiments confirm key intuitive expectations, e.g. that SAVAT between on-chip instructions and off-chip memory accesses tends to be higher than between two on-chip instructions. However, we find that particular instructions, such as integer divide, have much higher SAVAT than other instructions in the same general category (integer arithmetic), and that last-level-cache hits and misses have similar (high) SAVAT. Overall, we confirm that our new metric and methodology can help discover the most vulnerable aspects of a processor architecture or a program, and thus inform decision-making about how to best manage the overall side channel vulnerability of a processor, a program, or a system.

关键词： cryptography decision making program processors SAVAT decision-making electromagnetic emanation measurement instruction-level events laptop systems measurement equipment off-chip memory accesses on-chip instructions processor architecture program execution side channel vulnerability side-channel signal available to attacker single-instruction difference Area measurement Frequency measurement Instruments Measurement errors Measurement uncertainty Time measurement EM emanations computer security measurements metrics side channel vulnerability assessment Processor Architectures side channel measuring instruments program processors area measurement time measurement frequency measurement Computer Security Risk estimation measurement uncertainty Error measure Metronidazole cryptography decision making program execution

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