3D or multi-dimensional medical image reconstruction is attracting more and more attention in modern era. Rapid volumetric image reconstruction is of paramount importance to clinicians for prompt diagnosis and analysi...
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ISBN:
(纸本)9783642038815
3D or multi-dimensional medical image reconstruction is attracting more and more attention in modern era. Rapid volumetric image reconstruction is of paramount importance to clinicians for prompt diagnosis and analysis of complex tissue alternations. However, due to a high demand on computation for either the analytical or iterative image reconstruction algorithms, it is almost impossible to meet the requirement of real-time reconstruction. On the other hand, with high computing capability and broad banding characteristic, recently multi-core processors provide a new possibility and hopeful start for some of the most computation-demanding application such as medical imaging, digital media and entertainment equipment. This study aims to parallelize an analytical 3D CT image reconstruction algorithm, the so-called FDK method and to implement it on an existing multi- core platform system, towards a real- time 3D medical image reconstruction algorithm, the coding optimizations and a comparative results of run time savings are described.
Performance evaluation is critical for the minimization of design cost, It consists of two parts: modeling the underlying hardware engine and evaluating the performance of the application code for the model developed ...
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Performance evaluation is critical for the minimization of design cost, It consists of two parts: modeling the underlying hardware engine and evaluating the performance of the application code for the model developed in the first part, In this paper, we propose a new parameterized model for application-specific architectures and present a retargetable scheduler for performance evaluation, The model, different from those proposed previously, reflects comprehensive architectural characteristics that affect hardware parallelism, The scheduler, distinguished from previous ones, takes into account not only functional and storage unit resources but also interconnect resources during the performance evaluation, The new architecture model, together with the retargetable scheduler, enables designers to accurately evaluate the performance of a variety of ASIC and ASIP architectures.
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