检索结果-内蒙古大学图书馆

IEEE SPECTRUM 1987年第9期24卷 36-41页

作者： HOWE, CD MOXON, B BBN Adv. Comp. Inc.

To map a problem onto a parallel architecture, the programmer must first divide the problem into segments that will execute in parallel, then determine how the processors will communicate and synchronize with one another. This same procedure is followed no matter what the problem is and no matter which hardware will execute the program.

关键词： program processors Synchronization Computers Registers Computer architecture Switches Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Retrospecting Available CPU Resources: SMT-Aware Scheduling to Prevent SLA Violations in Data Centers

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第1期36卷 67-83页

作者： Liao, Haoyu Liu, Tong-yu Guo, Jianmei Huang, Bo Yang, Dingyu Ding, Jonathan East China Normal Univ Sch Data Sci & Engn Shanghai 200062 Peoples R China TRE Alibaba Grp Hangzhou 311121 Zhejiang Peoples R China SATG Intel Shanghai 200131 Peoples R China

The article focuses on an understudied yet fundamental problem: existing methods typically average the utilization of multiple hardware threads to evaluate the available CPU resources. However, the approach could underestimate the actual usage of the underlying physical core for Simultaneous Multi-Threading (SMT) processors, leading to an overestimation of remaining resources. The overestimation propagates from microarchitecture to operating systems and cloud schedulers, which may misguide scheduling decisions, exacerbate CPU overcommitment, and increase Service Level Agreement (SLA) violations. To address the potential overestimation problem, we propose an SMT-aware and purely data-driven approach named Remaining CPU (RCPU) that reserves more CPU resources to restrict CPU overcommitment and prevent SLA violations. RCPU requires only a few modifications to the existing cloud infrastructures and can be scaled up to large data centers. Extensive evaluations in the data center proved that RCPU contributes to a reduction of SLA violations by 18% on average for 98% of all latency-sensitive applications. Under a benchmarking experiment, we prove that RCPU increases the accuracy by 69% in terms of Mean Absolute Error (MAE) compared to the state-of-the-art.

关键词： Hardware Data centers Cloud computing Servers Processor scheduling program processors Monitoring Message systems Benchmark testing Accuracy SMT interference data center QoS microarchitecture latency-sensitive applications

来源：评论

学校读者我要写书评

暂无评论

Response Time Analysis With Cause-Effect Chain Considering DAG Structure and High-Load Tasks

引用

IEEE ACCESS 2025年 13卷 21557-21568页

作者： Kobayashi, Tomoya Okamura, Ryo Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama 3388570 Japan

Recent developments in autonomous driving systems highlight the significance of response time analysis. In autonomous driving systems, the complexities of response time analysis stem from different periods of tasks, tasks with high computational demands (high-load tasks), and Directed Acyclic Graph (DAG) structures. Although Cause-Effect Chain can consider tasks that are activated at different periods, there is no method that can handle high-load tasks. This paper proposes an allocation algorithm that assigns multiple processor cores to a single task and response time analysis using the Cause-Effect Chain in systems that include high-load tasks is realized. In addition, this paper extends a response time bound of Cause-Effect Chain, and proposes a response time bound of systems with DAG structures. The proposed algorithm and the proposed response time bound are evaluated by task sets generated from measured autonomous driving data. The evaluation results show that the proposed algorithm consistently indicates higher acceptance rates than existing algorithms. Furthermore, the proposed response time bound for the DAG can estimate response times that are shorter than existing bounds.

关键词： Time factors program processors Autonomous vehicles Processor scheduling Directed acyclic graph Periodic structures Interference Gold Registers Point cloud compression Cause-effect chain DAG many-core processors parallelization

来源：评论

学校读者我要写书评

暂无评论

Accelerating Sparse Tensor Decomposition Using Adaptive Linearized Representation

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第5期36卷 1025-1041页

作者： Laukemann, Jan Helal, Ahmed E. Anderson, S. Isaac Geronimo Checconi, Fabio Soh, Yongseok Tithi, Jesmin Jahan Ranadive, Teresa Gravelle, Brian J. Petrini, Fabrizio Choi, Jee Fedrich Alexander Univ Erlangen Nurnberg D-91054 Erlangen Germany Erlangen Natl High Performance Comp Ctr D-91054 Erlangen Germany Intel Labs Santa Clara 95054 CA USA Univ Oregon Eugene OR USA Lab Phys Sci Ft George G Meade MD 20755 USA

High-dimensional sparse data emerge in many critical application domains such as healthcare and cybersecurity. To extract meaningful insights from massive volumes of these multi-dimensional data, scientists employ unsupervised analysis tools based on tensor decomposition (TD) methods. However, real-world sparse tensors exhibit highly irregular shapes and data distributions, which pose significant challenges for making efficient use of modern parallel processors. This study breaks the prevailing assumption that compressing sparse tensors into coarse-grained structures (i.e., tensor slices or blocks) or along a particular dimension/mode (i.e., mode-specific) is more efficient than keeping them in a fine-grained, mode-agnostic form. Our novel sparse tensor representation, Adaptive Linearized Tensor Order (${\sf ALTO}$ALTO), encodes tensors in a compact format that can be easily streamed from memory and is amenable to both caching and parallel execution. In contrast to existing compressed tensor formats, ${\sf ALTO}$ALTO constructs one tensor copy that is agnostic to both the mode orientation and the irregular distribution of nonzero elements. To demonstrate the efficacy of ${\sf ALTO}$ALTO, we accelerate popular TD methods that compute the Canonical Polyadic Decomposition (CPD) model across different types of sparse tensors. We propose a set of parallel TD algorithms that exploit the inherent data reuse of tensor computations to substantially reduce synchronization overhead, decrease memory footprint, and improve parallel performance. Additionally, we characterize the major execution bottlenecks of TD methods on multiple generations of the latest Intel Xeon Scalable processors, including Sapphire Rapids CPUs, and introduce dynamic adaptation heuristics to automatically select the best algorithm based on the sparse tensor characteristics. Across a diverse set of real-world data sets, ${\sf ALTO}$ALTO outperforms the state-of-the-art approaches, achieving more than an or

关键词： Tensors Memory management Vectors Indexes Social networking (online) program processors Data mining Costs Synchronization Heuristic algorithms Sparse tensors tensor decomposition ALTO MTTKRP CP-APR poisson tensor decomposition alternating poisson regression multi-core CPU sapphire rapids

来源：评论

学校读者我要写书评

暂无评论

A Decade in Software-Based Side and Covert Channel Attacks and Countermeasures: A Survey

引用

IEEE ACCESS 2025年 13卷 56587-56606页

作者： Vasilas, Teodora Brad, Remus Lucian Blaga Univ Sibiu Comp Sci Elect & Elect Engn Dept Sibiu 550024 Romania

As technology continues to evolve, it provides significant benefits, such as seamless access to information, while also introducing critical security challenges, including privacy vulnerabilities and the rapid spread of misinformation. One major class of security threats involves software-based attacks, divided in side-channel attacks, which exploit unintended information leakage, and covert-channel attacks, which establish unauthorized communication pathways to bypass security policies. This survey provides a comprehensive review of the most cited attacks of these types in the past decade, along with their associated countermeasures. We classify the attacks and countermeasures based on the targeted system component and fundamental attack mechanisms. In addition, we conduct a comparative analysis of the attacks, considering key aspects such as attack methodology, targeted algorithms, victim system environment, reliability, performance impact, and mitigation strategies. Furthermore, we examine defense mechanisms, assessing their effectiveness, computational overhead, and applicability across various attack scenarios. Finally, we discuss emerging trends in attack techniques and countermeasures, highlighting open challenges and future research directions to secure modern computing systems.

关键词： Encryption Software program processors Transient analysis Monitoring Hardware Transforms Threat modeling Covert-channel attacks CPU security side-channel attacks survey side-channel attacks survey

来源：评论

学校读者我要写书评

暂无评论

RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V processors Design and Verification

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第4期72卷 1668-1678页

作者： Xu, Lida Cao, Zewen Zhao, Hualong Peng, Zhuo Miao, Yuchi Zhuang, Chunan Ruan, Hongrui Dong, Yuying Zeng, Chuanbin Li, Bo Luo, Jiajun Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Chinese Acad Sci Key Lab Sci & Technol Silicon Devices Beijing 100029 Peoples R China Beijing Inst Open Source Chip Beijing 100080 Peoples R China Chinese Acad Sci Inst Comp Technol Beijing 100029 Peoples R China Peng Cheng Lab Shenzhen 518055 Guangdong Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.

关键词： program processors Hardware Chip scale packaging Design methodology Costs Object oriented modeling Complexity theory Testing Registers Prototypes Agile methodology object-oriented hardware RISC-V low-cost integration verification open source

来源：评论

学校读者我要写书评

暂无评论

Partitioned Scheduling With Shared Resources on Imprecise Mixed-Criticality Multiprocessor Systems

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第1期44卷 65-76页

作者： Zhang, Yi-Wen Ma, Jin-Peng Gu, Zonghua Huaqiao Univ Coll Comp Sci & Technol Xiamen 361021 Peoples R China Hofstra Univ Dept Comp Sci Hempstead NY 11549 USA Umea Univ Dept Appl Phys & Elect S-90187 Umea Sweden

Both resource access protocols and real-time scheduling algorithms have been extensively studied in classic embedded real-time systems. However, there has been relatively little attention given to the resource access protocol and real-time scheduling algorithms in mixed-criticality systems. In this article, we pay attention to the problem of scheduling an imprecise mixed-criticality (IMC) taskset on a multiprocessor platform with shared resources. First, we propose an IMC with MSRP (IMC-MSRP) resource access protocol, which ensures mutually exclusive access to the shared resources for the tasks. Second, we propose the schedulability test based on the IMC-multiprocessor stack resource policy (MSRP) for a given task-to-processor mapping method. Third, we propose a feasible task-to-processor mapping algorithm called resource-aware criticality-unaware worst-fit decreasing (RA-CU-WFD), which first assigns tasks sharing the same resources to the same processor to reduce the global waiting time of the tasks and thus improve the schedulability ratio of the system. And then assigns tasks based on the criticality-unaware worst-fit decreasing (CU-WFD) algorithm. Finally, we conduct experiments using the synthetic tasksets, and the experimental results show that the RA-CU-WFD outperforms the other approaches in terms of the schedulability ratio.

关键词： Task analysis program processors Job shop scheduling Access protocols Scheduling algorithms Quality of service Partitioning algorithms Imprecise mixed-criticality (IMC) multicore partitioned scheduling shared resource

来源：评论

学校读者我要写书评

暂无评论

High-Sensitivity, Low-Power IR-UWB Radar Transceiver With Self-Interference Resistance for Child Presence Detection and Precision Positioning

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2025年第4期60卷 1150-1161页

作者： Seok, Hyun-Gi Kim, Wan Kim, Sinyoung Lee, Jae-Keun Lee, Geunhaeng Kim, Chanho Kim, Wonkang Cho, Jongpil Bae, Seungyong Cho, Youngsea Jung, Wonjun Kim, Junhyeong Kang, Sumin Na, Hyeokju Kang, Byoungjoong Han, Honggul Kang, Hoon Ahn, Chiyoung Jung, Sukjin Sung, Hyukjun Oh, Seunghyun Lee, Jongwoo Kim, Joonsuk Samsung Elect Syst LSI Business Hwaseong Si 18448 Gyeonggi Do South Korea Incheon Natl Univ Dept Informat & Telecommun Engn Incheon 22012 South Korea

This article presents a radar-enabled impulse radio ultrawideband (IR-UWB) system by adopting a self-interference-resistant RF transceiver. It demonstrates that child presence detection (CPD) using IR-UWB radar is feasible through the implementation of a radar system that includes physical (PHY), media access control (MAC), and application (APP) processors. The RF transceiver shows high receiver (RX) sensitivity and high transmitter (TX) peak power with low power. In addition, a radar-dedicated TX is used to improve the TX signal isolation to the RX. To achieve the high RX chain gain and low noise figure (NF) of RX, an RX front end (RX-FE) [low-noise amplifier (LNA) and voltage-to-current (V2I)] with a 50% duty cycle local oscillator (LO) is implemented. Furthermore, a notch pulse shaping filter (PSF) technique is proposed to meet spectrum emission mask (SEM) specifications with low power consumption. An LNA with wide gain ranges is also proposed to improve the sensitivity and support various applications related to radar and positioning applications. The UWB transceiver achieves -96.5-dBm sensitivity at BPRF 6.81 Mb/s and 14-dBm TX peak power and supports radar operation with UWB channels 5 and 9.

关键词： Transceivers Ultra wideband radar Radio frequency Radar Gain program processors Radar antennas Sensitivity Power demand Distance measurement Angle-of-arrival (AoA) child presence detection (CPD) IEEE 802.15.4/4z impulse radio ultrawideband (IR-UWB) low-noise amplifier (LNA) noise figure (NF) notch filter radar receiver (RX) self-interference sensitivity spectrum emission mask (SEM) time-of-arrival (ToA) transceiver transmitter (TX) UWB

来源：评论

学校读者我要写书评

暂无评论

Noise Suppression Method With Low-Complexity Noise Estimation Model and Heuristic Noise-Masking Algorithm for Real-Time Processing of Robot Vacuum Cleaners

引用

IEEE ACCESS 2025年 13卷 789-801页

作者： Shin, Seunghyeon Kim, Minhan Jeon, Inkoo Song, Ju-Man Park, Yongjin Son, Jungkwan Lee, Seokjin Kyungpook Natl Univ Sch Elect & Elect Engn Daegu 41566 South Korea LG Elect Adv Robot Lab Seoul 07336 South Korea Kyungpook Natl Univ Sch Elect Engn Daegu 41566 South Korea

Noise suppression in a high-level noise environment using a low-complexity method is challenging. This study proposes a low-complexity noise suppression algorithm for robot vacuum cleaner processors. We collected working noise from a robot vacuum cleaner along with speech signals and developed a method to extract the desired speech signal while estimating the noise. Our approach estimates the noise in the existing signal and converts it into the desired signal. In addition, we designed a low-complexity neural network capable of operating on mobile processors. The evaluation results demonstrate that our method achieves a performance comparable to that of highly computational methods. Notably, our method maintains superior performance when the intensity of the desired signal is low, and its performance is less degraded than that of other methods. It exhibits less degradation than existing methods, and in contrast to other neural networks, it avoids generating incorrect signals. Furthermore, we simplified the neural network architecture reducing its size by approximately 25% with minimal performance loss.

关键词： Noise Robots Noise reduction Neural networks Complexity theory Collision avoidance Acoustics Signal to noise ratio program processors Spectrogram Source separation low-complexity low-SNR machine learning mask estimation mono channel neural network noise suppression robot vacuum cleaner

来源：评论

学校读者我要写书评

暂无评论

PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第2期33卷 525-536页

作者： Wang, Yuanbo Chang, Liang Wang, Jingke Zhao, Pan Zeng, Jiahao Zhao, Xin Hao, Wuyang Zhou, Liang Tan, Haining Han, Yinhe Zhou, Jun Univ Elect Sci & Technol China Sch Informat & Commun Engn Chengdu 611731 Peoples R China Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China

Computing-in-memory (CIM) architecture has become a promising solution to improve the parallelism of the multiply-and-accumulation (MAC) operation for artificial intelligence (AI) processors. Recently, revived CIM engine partly relieves the memory wall issue by integrating computation in/with the memory. However, current CIM solutions still require large data movements with the increase of the practical neural network model and massive input data. Previous CIM works only considered computation without concern for the memory attribute, leading to a low memory computing ratio. This article presents a static-random access-memory (SRAM)-based digital CIM macro supporting pipeline mode and computation-memory-aware technique to improve the memory computing ratio. We develop a novel weight driver with fine-grained ping-pong operation, avoiding the computation stall caused by weight update. Based on our evaluation, the peak energy efficiency is 19.78 TOPS/W at the 22-nm technology node, 8-bit width, and 50% sparsity of the input feature map.

关键词： In-memory computing Neural networks Common Information Model (computing) Energy efficiency Computer architecture Pipelines program processors Indexes Convolution Engines Computing-in-memory (CIM) digital circuit low power multiply-and-accumulator pipeline computing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：