In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmablegate ...
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In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 x 32 network connections, is designed on a chip (4.73 mm x 4.73 mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.
A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built...
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A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events.
This study examines the single-event response of the Xilinx 20 nm Kintex UltraScale Field-programmable gate array irradiated with heavy ions. Results for single-event latchup and single- event upset on configuration S...
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ISBN:
(纸本)9781467376419
This study examines the single-event response of the Xilinx 20 nm Kintex UltraScale Field-programmable gate array irradiated with heavy ions. Results for single-event latchup and single- event upset on configuration SRAM cells and Block RAM memories are provided.
This paper describes a real-time correlation tracker realized with Field programmable gate array(FPGA). Primarily a method for correlation tracking target has been developed. The main point of this method is to presen...
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ISBN:
(纸本)0819425869
This paper describes a real-time correlation tracker realized with Field programmable gate array(FPGA). Primarily a method for correlation tracking target has been developed. The main point of this method is to present the reference pattern updating methods we implemented. Then, information on system hardware is given. The correlation tracking circuit is realized by FPGA so autotracker is small, low cost, and it could be used for real time application. Subsequently, system software can be found. System operation is controlled by high speed Digital Signal Processor(DSP) TMS320C30. In the end, the results of field-tests with our real-time correlation autotracker show that under complex background and foreground, such as clouds, trees, gasses, our approach can track a flying plane or a moving vehicle steadily.
An IBM PC-AT interface for data acquisition from diode arrays is described. It was developed for use in an extended energy loss fine structure (EXELFS) spectrometer, where sometimes two diode arrays (containing EXELFS...
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An IBM PC-AT interface for data acquisition from diode arrays is described. It was developed for use in an extended energy loss fine structure (EXELFS) spectrometer, where sometimes two diode arrays (containing EXELFS and low-loss spectra) need simultaneous scanning. The system operates as a multiscaler, allowing two processes to be recorded at the same time. The interface was designed using a programmable gate array (an 1800 gate-equivalent logic cell array from XILINX) to implement most of the digital circuitry and a 12-b ADC to sample the analog inputs. A 12-b DAC was used for analog outputs and for diagnostic testing purposes. The interface hardware was given a general design so that it could be used in other similar applications.
Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, ...
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Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.
This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel le...
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This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel level parallelism is exploited in an FPGA design for the bottleneck portion of the application. The implementation of this design achieved a speedup of 21 compared to running on the host processor. The paper then describes an FPGA resource manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can be reconfigured for other purposes. The IR ATR application was ported to work with the RM and has been shown to adapt to the amount of reconfigurable hardware that is available at the time the application is executed.
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considere...
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In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.
A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also cre...
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A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also creates challenges with respect to security. Architecture for two-factor authentication is designed with low-power, area and with less- human intervention. The proposed model consists of hybrid physical unclonable functions (PUFs) and finite state machine (FSM), which is used to secure the chip and intellectual property (IP) respectively. The PUFs are most often used in recent security applications such as IP protection, IC metering, hardware signature, and obfuscation. This application needs a complex algorithm with a database which consumes more cost and time. In this paper, we have proposed an authentication model consisting of strong and weak PUF with an FSM which can be used for IoT applications. The main focus of this proposal is to authenticate hardware and software IP in circuits. The Experimental evaluation illustrates that the area and power consumed are 5% and 9%, respectively, for authenticating 26 IPs with no false acceptance ratio (FAR) and 1% false rejection ratio (FRR).
The aim of this paper is to outline a new approach in the digital realization of Boolean Neural Networks. It is based on programmable gate array technology (PGA). Each cell in the gatearray performs the binary additi...
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The aim of this paper is to outline a new approach in the digital realization of Boolean Neural Networks. It is based on programmable gate array technology (PGA). Each cell in the gatearray performs the binary addition/subtraction function. Space iteration of such digital circuit enables the calculation of all output functions of neurons in the network. The topology of the network influences the connections between neurons and therefore the connections in PGA. This approach offers definite advantages over other solutions. Regular architecture with full connectivity, modularity of completely digital circuits, and possible use of programming support are some of the most important features of the proposed digital realization.
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