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IEEE Radiation Effects Data Workshop (REDW)

作者： Lee, David S. Allen, Gregory R. Swift, Gary Cannon, Matthew Wirthlin, Michael George, Jeffrey S. Koga, Rokutaro Huey, Kangsen Sandia Natl Labs Albuquerque NM 87123 USA NASA Jet Prop Lab Pasadena CA 91109 USA Swift Engn & Radiat Serv LLC San Jose CA 95124 USA Brigham Young Univ Dept Elect & Comp Engn Ctr High Performance Reconfigurable Comp Provo UT 84602 USA Aerosp Corp El Segundo CA 90245 USA Xilinx Inc San Jose CA 95124 USA

This study examines the single-event response of the Xilinx 20 nm Kintex UltraScale Field-programmable gate array irradiated with heavy ions. Results for single-event latchup and single- event upset on configuration S... 详细信息

ISBN: (纸本)9781467376419

关键词： ion irradiation Field programmable gate arrays heavy ions programmable gate array Single event upsets Irradiation Newton meter latchlocks Single shot characterization CCDC26 gene random access machine FAM103A1 gene

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Big data application in exchange rate financial prediction platform based on FPGA and human -computer interaction

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MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103626-103626页

作者： Huang, Ping Hunan Univ Sch Econ & Trade Changsha 410079 Hunan Peoples R China

A prediction is a statement about the financial market. The financial market prediction may lack sufficient reasons or any good stock market analysis. The financial prediction may be correct or inaccurate on any given occasion, or average, Model-based or information. The financial prediction is made by various methods, including hundreds of economic evaluation and test systems, which are Observable in the gate array. The Digital signal processing system and IoT (Internet of thing) for exchange rate finical perdition platform in the previous method. The previous method is difficulty in lower investment to reduce inflation and false value setting. The proposed method is based on programmable gate and learning for finical predication. A critical challenge of financial forecasting issues, along with opportunities that arise from the unique characteristics of financial data, signal-to-noise ratios, persistent predictors, predictive instability and environmental predictability resulting from competitive pressure and investors learning. The machine approaches for predicting the mean, variance, and probability distribution of asset returns. programmable gate array covers how to evaluate financial forecasts, which leads to data mining concerns, taking into account the possibility that numerous forecast models are being considered.

关键词： Exchange rate Financial prediction platform programmable gate array

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Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2021年第7期33卷 1-1页

作者： Hariharan, I Kannan, M. Anna Univ Dept Elect Engn MIT Campus Chennai Tamil Nadu India

Field programmable gate arrays (FPGAs) are preferred in the modern embedded system to accelerate the performance of the entire system. However, the FPGAs are liable to suffer from reconfiguration overheads. These overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and due to the improper management of tasks during execution. To reduce these overheads, two algorithms are proposed. Both the algorithms focus on the prefetch heuristics, reuse technique, and an optimal mapping of tasks over the available memories. However, in terms of reusing technique, algorithm-1 uses least recently used (LRU) policy and algorithm-2 uses the optimal replacement policy (considering the vitality of the reconfigurable units (RUs)). Simulation results are obtained for both the algorithms. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on the proposed algorithms. Also, the two algorithm results are compared and analyzed. For this purpose, the experiments included smaller and larger task graphs. In the case of smaller task graphs, algorithm-2 outperforms algorithm-1 in reducing reconfiguration overheads. In larger task graphs, algorithm-1 produces better results compared to algorithm-2.

关键词： configuration mapping field‐ programmable gate array multimedia application optimal‐ replacement policy reconfiguration overheads scheduling

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Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2019年第4期35卷 543-558页

作者： Kokila, J. Ramasubramanian, N. Natl Inst Technol Dept Comp Sci & Engn Tiruchirappalli Tamil Nadu India

A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also creates challenges with respect to security. Architecture for two-factor authentication is designed with low-power, area and with less- human intervention. The proposed model consists of hybrid physical unclonable functions (PUFs) and finite state machine (FSM), which is used to secure the chip and intellectual property (IP) respectively. The PUFs are most often used in recent security applications such as IP protection, IC metering, hardware signature, and obfuscation. This application needs a complex algorithm with a database which consumes more cost and time. In this paper, we have proposed an authentication model consisting of strong and weak PUF with an FSM which can be used for IoT applications. The main focus of this proposal is to authenticate hardware and software IP in circuits. The Experimental evaluation illustrates that the area and power consumed are 5% and 9%, respectively, for authenticating 26 IPs with no false acceptance ratio (FAR) and 1% false rejection ratio (FRR).

关键词： System-on-a-chip design Field programmable gate array Arbiter PUF Butterfly PUF Finite state machine Two-factor authentication Hardware security and IP protection

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Design of Fractional PID Control System for BLDC motor Based on FPGA 30

Design of Fractional PID Control System for BLDC motor Based...

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30th Chinese Control and Decision Conference (CCDC)

作者： Zhang, Fan Li, Zhuangju Beijing Univ Civil Engn & Architecture Inst Elect & Informat Engn Beijing 100044 Peoples R China

ISBN: (纸本)9781538612446

In this pape, pricision brushless DC motor control system based on field programmable gate array (FPGA) was designed. The system consists of two parts: FPGA and peripheral circuits. FPGA as the control core of the whole circuit, through the hardware programming language VerilonFIDE programming FPGA internal hardware circuit to complete fractional PID control algorithm, based on fractional PID control mode to achieve the appropriate duty cycle PWM output controller design. The simulation results show that the fractional-order PID controller based on FPGA has the advantages of simple structure, flexible control and strong anti-interference ability, meanwhile meets the actual requirements of motor speed regulation.

关键词： programmable gate array Brushless DC Motor PWM Fractional PID

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Design of a Tritium-In-Air Monitor Using Field-programmable gate arrays

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JOURNAL OF NUCLEAR ENGINEERING AND RADIATION SCIENCE 2016年第4期2卷 044506-1-044506-3页

作者： McNelles, Phillip Lu, Lixuan Univ Ontario Inst Technol ASME 2000 Simcoe St North Oshawa ON L1H 7K4 Canada Univ Ontario Inst Technol 2000 Simcoe St North Oshawa ON L1H 7K4 Canada

Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.

关键词： programmable gate array Health hazards Field programmable gate arrays tritium C-14 Health physics criterion function Radiation Interaction Particle detectors laboratory procedure pulse measurement moderators updated design MONITOR

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Design of Fractional PID Control System for BLDC motor Based on FPGA

Design of Fractional PID Control System for BLDC motor Based...

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第30届中国控制与决策会议

作者： Fan Zhang Zhuangju Li Beijing University of Civil Engineering and Architecture Institute of electrical and information engineering

In this pape, pricision brushless DC motor control system based on field programmable gate array(FPGA) was designed. The system consists of two parts: FPGA and peripheral circuits. FPGA as the control core of the whole circuit, through the hardware programming language VerilogHDL programming FPGA internal hardware circuit to complete fractional PID control algorithm, based on fractional PID control mode to achieve the appropriate duty cycle PWM output controller design. The simulation results show that the fractional-order PID controller based on FPGA has the advantages of simple structure, flexible control and strong anti-interference ability, meanwhile meets the actual requirements of motor speed regulation.

关键词： programmable gate array Brushless DC Motor PWM Fractional PID

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Variable-Latency Signed Addition on FPGAs 25

Variable-Latency Signed Addition on FPGAs

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25th International Conference on Field programmable Logic and Applications

作者： Cilardo, Alessandro Univ Naples Federico II Dept Elect Engn & Informat Technol Via Claudio 21 I-80125 Naples Italy

ISBN: (纸本)9781467381239

Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands have equiprobable independent bits, which is rarely the case in real applications due to sign-extension, or they can handle the case of signed numbers at the price of a considerable area overhead. Furthermore, many existing approaches require ad-hoc schemes preventing the reuse of standard adders typically available as optimized library components in many technologies, most notably Field-programmable gate arrays. This paper introduces an innovative scheme for speculative addition that effectively addresses both problems, yielding fast and low-area circuits able to handle sign-extended numbers speculatively and only made of optimized carry-propagation adders based on fast carry circuitry as basic building blocks.

关键词： Field programmable gate arrays adders Fasting Electric circuits Signed Addition reaction reuse programmable gate array Handles operand basic component

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Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

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JAPANESE JOURNAL OF APPLIED PHYSICS 2015年第9期54卷 9MA06.1-9MA06.1页

作者： Seto, Daisaku Watanabe, Minoru Shizuoka Univ Dept Elect & Elect Engn Hamamatsu Shizuoka 4328561 Japan

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 x 10(4) times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and highspeed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation. (C) 2015 The Japan Society of Applied Physics

关键词： Field programmable gate arrays Logic arrays configurability Radiation Tolerance programmable gate array holographic storage Radiation Radiation hardening

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Mono-instruction set computer architecture on a 3D optically reconfigurable gate array

Mono-instruction set computer architecture on a 3D optically...

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IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

作者： Ito, Hiroyuki Watanabe, Minoru Shizuoka Univ Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9781479923113;9781479923137

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecondorder. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

关键词： dynamic reconfiguration Logic arrays Computer Architecture Processor Performance programmable gate array Very large scale integration holographic storage configurability layer number Through-silicon vias Taura syndrome virus of marine penaeid shrimp NANOSECOND

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