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A LOW-POWER PLA FOR A SIGNAL PROCESSOR

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1991年第2期26卷 107-115页

作者： LINZ, AR Communication Products Division Advanced Micro Devices Inc. Austin TX USA

The architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment are presented. The PLA achieves low power consumption by a combination of pipelining, use of a NAND-NOR co... 详细信息

关键词： programmable logic arrays Signal processing Digital signal processing Filters Power dissipation Algorithms Energy consumption CMOS technology Signal design Codecs

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C-CONFIGURABILITY AND BUILT-IN-TEST OF RECONFIGURABLE PROCESSOR ARRAY INTERCONNECTION NETWORKS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1992年第5期39卷 302-311页

作者： HENLING, B SOMA, M GE CTR RES & DEVSCHENECTADYNY 12345

This paper describes a general purpose interconnection switch applicable to reconfigurable architectures. The switch has been used in the design of reconfigurable architectures and in processor arrays that require reconfigurable interconnections. The reconfigurable switch has the desirable properties that it is both scalable and C-testable. Furthermore, the switch is shown to be C-configurable;that is, the number of configurations required to test a network of switches is independent of the size of the network. Criteria are given for selecting BIT techniques and implementations for reconfigurable architectures. Algorithms are presented for generating configuration values and test data. Finally, the authors' BIT implementation is then presented and analyzed and is shown to provide 100% fault coverage for single S-A-O, S-A-1, bridging, and high impedance, permanent combinational faults.

关键词： Multiprocessor interconnection networks Switches Reconfigurable architectures Testing Signal processing algorithms Communication switching programmable logic arrays Circuit faults Integrated circuit interconnections Digital signal processing

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DESIGN AND APPLICATION OF AN OPTIMIZING XROM SILICON COMPILER

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第12期8卷 1267-1275页

作者： LINDERMAN, RW ROSSBACH, PC GALLAGHER, DM USAF INST TECHNOLDEPT ELECT & COMP ENGNWRIGHT PATTERSON AFBOH 45433

It is demonstrated that optimization techniques incorporated within a silicon compiler for read-only memories (ROMs) can achieve significant yield, power, and speed improvements by minimizing the number of transistors, drains, and metal interconnections in the ROM. Transistor minimization adopts a heuristic solution to the NP-complete graph partitioning problem with a powerful technique applicable to various ROM design styles and technologies. If diffusion mask personalization is permitted, the design can be further improved by solving the traveling salesman problem to minimize transistor source/drain regions. In table look-up ROMs compiled for 3- and 1.2- mu m CMOS with diffusion mask programming, the compiler eliminated over 45% of the transistors and drains. Test results show that 3- mu m CMOS ROMs have access times between 50 and 70 ns. ROMs with 1.2- mu m features achieve simulated access times below 20 ns. A simple interface allows the optimizing compiler to work easily with other CAD tools such as microcode assemblers.< >

关键词： Design optimization Optimizing compilers Silicon compiler Read only memory programmable logic arrays Testing Chip scale packaging Decoding CMOS technology

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FPGA and CPLD architectures: A tutorial

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IEEE DESIGN & TEST OF COMPUTERS 1996年第2期13卷 42-57页

作者： Brown, S Rose, J University of Toronto Canada

This tutorial surveys commercially available, high-capacity field-programmable devices. The authors describe the three main categories of FPDs: simple and complex programmable logic devices, and field-programmable gate arrays. They then give architectural details of the most important chips and example applications of each type of device.

关键词： Tutorial Field programmable gate arrays programmable logic arrays Flip-flops Manufacturing logic devices Feedback logic functions Propagation delay Feeds

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Research on Anomaly Suppression Method of Plasma-Sheath-Covered Reentry Target

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IEEE TRANSACTIONS ON PLASMA SCIENCE 2022年第6期50卷 1765-1774页

作者： Ding, Yi Bai, Bowen Niu, Gezhao Li, Xiaoping Liu, Yanming Xidian Univ Sch Aerosp Sci & Technol Key Lab Environm Phys Xian 710071 Peoples R China

As the reentry target passes through the atmosphere at hypersonic velocity, its surface is covered with a plasma sheath. The plasma sheath produces an amplitude-phase modulation effect on the radar echo and increases the signal component of the radar echo, which seriously affects the radar's reliable detection of reentry target and leads to a series of abnormal radar detection problems. Through the radar echo model of the plasma-sheath-covered target, the multidomain characteristics of the echo signal are analyzed, and the electromagnetic (EM) shielding effect of the plasma sheath on EM waves is revealed. Based on the intrapulse Doppler frequency extraction technology, a design method of false target filter is proposed, which can effectively suppress false targets generated by the plasma sheath. Through the simulation analysis of single-period echo signals and multiperiod echo signals, the feasibility of the algorithm in this article is verified, and the reliability of the algorithm is verified by statistical experiment analysis, which lays a theoretical foundation for reliable radar detection of plasma-sheath-covered target.

关键词： Plasma sheaths Radar Doppler effect Radar cross-sections Radar detection programmable logic arrays Plasmas Electromagnetic (EM) shielding false target suppression filter intrapulse Doppler frequency plasma sheath radar echo

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A CMOS CHIP PAIR FOR DIGITAL TV

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第5期22卷 835-840页

作者： SUZUKI, S KAWAI, K MURAMATSU, K TOSHIBA CORP AUDIO VIDEO PROD ENGN LABISOGU KUYOKOHAMAJAPAN

A two-chip digital TV with the potential for 650 horizontal lines of resolution and implemented with 195 K transistors has been described. Both are fabricated in 1.5-/spl mu/m double-metal CMOS technology and assembled in plastic packages. The video processor with a 2 H one-transistor cell dynamic RAM line memory contains 140 K transistors in a 62-mm/SUP 2/ chip, operates up to 50 MHz, and dissipates 250 mW at 14.3 MHz. The synchronous processor dissipates 110 mW at 14.3 MHz.

关键词： Digital TV Signal processing CMOS technology logic design logic arrays programmable logic arrays Band pass filters Clamps Plastic packaging Frequency

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Scattering characteristics of a rectangular groove in a reactive surface

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 1995年第12期43卷 1450-1458页

作者： Buyukaksoy, A Birbir, F Erdogan, E ISTANBUL TECH UNIV FAC ELECT & ELECTR ENGNISTANBUL 80626TURKEY

The diffraction of a plane electromagnetic wave by a rectangular groove in a reactive plane is studied rigorously through the Fourier transform technique. The corresponding boundary value problem is Formulated into a modified Wiener-Hopf equation of the third kind whose approximate solution involves two sets of infinite number of unknown constants satisfying two infinite systems of linear algebraic equations. Numerical solutions of these systems are obtained for various values of the surface reactance and the sizes of the groove through which the effects of these parameters on the diffraction phenomenon are studied.

关键词： Fourier transforms boundary-value problems electromagnetic wave diffraction electromagnetic wave scattering linear algebra Fourier transform technique boundary value problem linear algebraic equations modified Wiener-Hopf equation numerical solutions pla electromagnetic wave diffraction rectangular slot diffraction Boundary value problems Scattering characteristics Electromagnetic wave scattering programmable logic arrays Fourier Transform Linear algebra

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Physical Layer Authentication in Spatial Modulation

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IEEE TRANSACTIONS ON COMMUNICATIONS 2023年第5期71卷 2947-2962页

作者： Xu, Yuntao Zhang, Jiaheng Zhang, Qihong Zhang, Peichang Huang, Lei Xie, Ning Lu, Jian Shenzhen Univ Coll Elect & Informat Engn State Key Lab Radio Frequency Heterogeneous Integr Shenzhen 518060 Peoples R China Shenzhen Univ Coll Elect & Informat Engn Guangdong Key Lab Intelligent Informat Proc Shenzhen 518060 Peoples R China Shenzhen Univ Coll Math & Stat Shenzhen Key Lab Adv Machine Learning & Applicat Shenzhen 518060 Peoples R China

Spatial Modulation (SM) is a promising low-complexity modulation scheme for Multiple-Input Multiple-Output (MIMO) systems. In this paper, we address the problem of authenticating the transmitter device in the SM. We propose an authentication approach for an SM system by using Physical-Layer Authentication (PLA) mechanisms because the PLA has the following advantages: high security and low complexity. Based on the features of an SM system, we propose two PLA schemes: PLA with Superimposed Authentication Tag (PLA-SAT) and PLA with Superimposed Imaginary authentication Tag (PLA-SIT). We provide performance analyses of our schemes over fading channels in terms of robustness, compatibility, and security. Moreover, we derive their closed-form expressions under both perfect and imperfect channel estimates, including the Probability of Detection (PD), Probability of False Alarm (PFA), and Average Error Probability (AEP). Although the two proposed schemes have the same robustness and security, the PLA-SIT scheme has better compatibility than the PLA-SAT scheme. Our schemes were implemented and extensive performance comparisons through simulations were conducted. We observe that the simulation results of the two proposed schemes perfectly match their corresponding theoretical analyses. The authentication accuracy of the two proposed schemes is close to one when the received SNR is greater than 20 dB and the security performances of the two proposed schemes improve as the variance of estimation errors increases.

关键词： Authentication programmable logic arrays Security Robustness Receivers Fading channels Symbols Physical-layer authentication spatial modulation MIMO compatibility security

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Influence of Temperature on Viscoelastic-Viscoplastic Behavior of Poly(lactic acid) Under Loading-Unloading

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POLYMER ENGINEERING AND SCIENCE 2017年第3期57卷 239-247页

作者： Dusunceli, Necmi Drozdov, Aleksey D. Theilgaard, Naseem Aksaray Univ Dept Mech Engn TR-68100 Aksaray Turkey Aalborg Univ Dept Mech & Mfg Engn DK-9220 Aalborg Denmark Danish Technol Inst Ctr Plast Technol DK-2630 Taastrup Denmark

Experimental data are reported on poly(lactic acid) (PLA) in tensile loading-unloading tests and relaxation tests under stretching and retraction at temperatures ranging from room temperature up to 508C. Two characteristic features of the time-dependent response of PLA are revealed: (i) with a decrease in minimum stress under retraction at a fixed temperature, relaxation curves change their shape from monotonically decaying with time (simple relaxation), to non-monotonic (mixed relaxation) to monotonically increasing (inverse relaxation) and (ii) with an increase in temperature, inverse relaxation after unloading down to the zero stress evolves into mixed relaxation with a pronounced shift of the peak position to smaller relaxation times. Constitutive equations are derived for the mechanical behavior of PLA, and adjustable parameters in the stress-strain relations are found by fitting the observations. Ability of the model to predict the time-dependent response under cyclic deformation is confirmed by numerical simulation. (C) 2016 Society of Plastics Engineers

关键词： stress-strain relations adjustable parameter Intercostal Retractions Constitutive equations time-dependent Relaxation programmable logic arrays relaxation Stretch UNLOADING Temperature LOADING AND UNLOADING poly(lactic acid) Mechanical properties

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Lightweight Cross-Domain Authentication Scheme for Securing Wireless IoT Devices Using Backscatter Communication

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IEEE INTERNET OF THINGS JOURNAL 2024年第12期11卷 22021-22035页

作者： Zhang, Guoqiang Hu, Qiwei Zhang, Yu Dai, Yueyue Jiang, Tao Res Ctr 6G Mobile Commun Sch Cyber Sci & Engn Wuhan 430074 Peoples R China

Cross-domain collaboration under wireless communication scenarios has gained traction in Internet of Things (IoT) applications. Authentication is essential for ensuring the security of wireless IoT devices (IoTDs). However, the existing cryptographic and physical-layer authentication schemes are unappealing in cross-domain scenarios due to the presence of resource-limited IoTDs, privacy concerns of cross-domain sharing, and the negative effect of malicious attackers. This article proposes FedScatter, a lightweight cross-domain authentication scheme for securing wireless IoTDs using backscatter communication. First, device identity signatures are constructed by harnessing passive signal features generated from feather-light backscatter tags, incurring negligible overhead. Subsequently, a federated learning model is designed to aggregate device identity information across domains while respecting device heterogeneity and data privacy. A novel parameter aggregation algorithm is proposed to bolster authentication resilience and against malicious attacks to avoid model pollution by powerful attackers with substantial hardware resources. A FedScatter prototype is implemented and evaluated, demonstrating significant improvements over state-of-the-art works in both true positive rate and false positive rate under various attacks.

关键词： Backscatter Communication system security programmable logic arrays Physical layer Internet of Things federated learning (FL) Internet of Things (IoT) security lightweight cross-domain authentication

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