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AN ALTERABLE programmable logic ARRAY

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年第5期20卷 1061-1066页

作者： MARCHAND, JFP Xerox Webster Research Center Webster NY USA

The NMOS alterable programmable logic array (APLA) performs the same logical function as a standard programmable logic array, but it can be programmed and reprogrammed electrically to change the logic function. Each term in the AND and OR array of the APLA can be individually enabled or disabled by writing a memory cell associated with it. The prototype array has 22 inputs, 22 outputs, and 64 product terms. The chip can be programmed through a standard microprocessor interface. The performance, operation, and layout of the PLA array; the basic dynamic memory cells; and the methods used to load and refresh the memory are described.

关键词： programmable logic arrays MOS devices Equations logic programming logic functions Writing logic arrays Read only memory logic design programmable logic devices

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MULTIPLE-VALUED CCD CIRCUITS

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COMPUTER 1988年第4期21卷 58-69页

作者： BUTLER, JT KERKHOFF, HG TWENTE UNIV TECHNOL IC TECHNOL & ELECTR GRPENSCHEDENETHERLANDS

The benefits and current state of the art of charge-coupled-device logic are examined. The fundamentals of CCD logic operations and basic CCD configurations are presented. programmable logic arrays are considered. The... 详细信息

关键词： CCD logic operations CCD multivalued logic cellular arrays charge-coupled device circuits charge-coupled-device logic integrated logic circuits logic design many-valued logics programmable logic arrays

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CORRELATION ESTIMATORS BASED ON SIMPLE NONLINEAR TRANSFORMATIONS

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1995年第6期43卷 1438-1444页

作者： SULLIVAN, MC WEGMAN, EJ GEORGE MASON UNIV CTR COMPUTAT STATFAIRFAXVA 22030

The computational cost of estimating correlations may be reduced by employing sums of simple nonlinear functions of the data. A quadruplex transformation is presented and the performance of the associated estimator is analyzed for real and complex Gaussian processes. With independent observations, the variance of the estimator is approximately 14% higher than that obtained by averaging lag products.

关键词： Signal processing algorithms Computational efficiency Signal processing Costs Random variables Application specific integrated circuits Field programmable gate arrays programmable logic arrays Performance analysis Gaussian processes

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Flexural, morphological and thermal properties of poly(lactic acid)/organo-montmorillonite nanocomposites

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POLYMERS & POLYMER COMPOSITES 2008年第4期16卷 263-270页

作者： Shyang, Chow Wen Kuen, Lok Sook Univ Sains Malaysia Sch Mat & Mineral Resources Engn Nibong Tebal 14300 Pulau Pinang Malaysia

Poly(lactic acid) (PLA)/organo-montmorillonite (OMMT) nanocomposites were prepared by using solution intercalation and melt intercalation methods. For solution intercalation method, toluene was used as solvent. For melt intercalation method, PLA/OMMT composites were prepared by using single-screw extruder. The flexural properties of PLA/OMMT composites have been studied by using three point bending tests. Comparisons between the flexural properties of PLA/OMMT nanocomposites prepared by both methods have been carried out. The microstructures of the PLA/OMMT nanocomposites were assessed by Field Emission Scanning Electron Microscopy (FESEM) and X-ray Diffraction (XRD) analysis. The thermal properties of PLA/OMMT nanocomposites have been characterized by using Differential Scanning Calorimeter (DSC). The flexural modulus of PLA/OMMT nanocomposites prepared by both solution intercalation and melt intercalation methods increased significantly by the addition of OMMT. For both methods, it was found that the optimum flexural properties of the PLA nanocomposites was achieved at 1 wt.% OMMT loading. The dispersion of OMMT in the PLA prepared by solution intercalation is better than that of melt intercalation method. This is attributed to the ease of intercalation of PLA chain into the OMMT layered silicate during the solution intercalation process. XRD results revealed that intercalation of OMMT layered silicate occurred in the PLA matrix.

关键词： poly(lactic acid) Nanocomposites Intercalation three-point bending Organo-modified montmorillonite programmable logic arrays FLEXURAL PROPERTIES Thermal properties

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Estimation of relative evapotranspiration from NOAA PAL to derive growth characteristics in India

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INTERNATIONAL JOURNAL OF REMOTE SENSING 2008年第11期29卷 3271-3293页

作者： Sarkar, Chaitali Bhattacharya, Bimal K. Gadgil, Alaka Mallick, Kanishka Patel, N. K. Parihar, J. S. ISRO Ctr Space Applicat Agr Forestry & Environm Grp Ahmadabad 380015 Gujarat India Univ Poona Dept Geog Pune 411007 Maharashtra India

Clear-sky dekadal relative evapotranspiration (RET) was derived using the surface energy-balance approach applied to 10-day composite NOAA PAL (8 km x 8 km) datasets over the Indian landmass. This was further used to differentiate between growth characteristics for an irrigated intensive agriculture over a northern India state (e. g. Punjab) and a rainfed ill-posed agriculture over a central India state (e. g. Madhya Pradesh) using time-series data sets for five growing years (June-April): 1996-1997, 1997-1998, 1998-1999, 1999-2000, and 2000-2001. The triangular scatter between RET and normalized difference vegetation index (NDVI) showed that the minimum RET increases linearly with NDVI producing a 'basal line' that represents relative canopy transpiration only. A clear distinction in scatter was found between the two contrasting agro-ecosystems showing a higher RET or root zone wetness in irrigated than rainfed systems. In rainfed rice-growing regions, an inverse correlation (0.6-0.75) was found between RET and the Keetch-Byram meteorological drought index (KBDI), and a substantial reduction in RET was also found in a sub-normal (2000) compared with a normal (1999) monsoon season. RET estimates were found to be most sensitive to atmospheric transmissivity followed by other land-surface radiation budget inputs, such as NDVI, LST, and albedo. Error propagation due to three surface parameters is the opposite of that for transmissivity. The maximum possible error in clear-sky NOAA PAL RET was estimated to be 12-15%. This test study would be helpful in deriving RET using optical and thermal data from a suite of current and future Indian geostationary satellite sensors for monitoring growing conditions.

关键词： Error propagation thermal analysis data LRIT1 gene Normalized Difference Vegetation Index (ndvi) SHCBP1 gene programmable logic arrays National Oceanic and Atmospheric Administration normalized difference vegetation index time series data

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A Rapid Design and Fabrication Method for a Capacitive Accelerometer Based on Machine Learning and 3D Printing Techniques

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IEEE SENSORS JOURNAL 2021年第16期21卷 17695-17702页

作者： Liu, Guandong Wang, Changhai Jia, Zhili Wang, Kexin Ma, Wei Li, Zhe Heriot Watt Univ Inst Sensors Signals & Syst Edinburgh EH14 4AS Midlothian Scotland Natl Inst Metrol Ctr Adv Measurement Sci Beijing 100029 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn State Key Lab Modern Opt Instrumentat Hangzhou 310027 Peoples R China Peking Univ Sch Elect Engn & Comp Sci Beijing 100871 Peoples R China

MEMS (Micro Electromechanical System) sensors have been increasingly used to detect human movements in health monitoring applications. Usually, a full cycle of design and fabrication of a MEMS sensor such as an accelerometer requires highly professional understanding of device functions and expertise in microfabrication process. However, the advent of internet of things (IoT) brings a large demand for low-cost and highly customizable sensors, which requires fast fabrication and flexible design, even by the customers with limited background knowledge in the device itself. In this work, we present the development of a rapid design and fabrication workflow for accelerometers by combining an artificial neural network (ANN) based inverse design method and a one-step 3D printing fabrication technique. The one-step 3D printing fabrication approach is based on a conductive composite material, a polylactic acid (PLA) polymer with carbon black. In device design, trained bidirectional ANNs were designed to predict the device performance from given design parameters and retrieve the design parameters from the customer requirements of the device performance. A capacitive accelerometer was then designed based on the retrieved geometric parameters and fabricated by an integrated 3D printing process without using any additional metallization and assembly processes. With a sensitivity of 75.2 mV/g and a good dynamic response, the 3D printed accelerometer was shown to be capable of detection and monitoring of human movements. The proposed rapid design and fabrication workflow provides an effective solution to customized and low-cost MEMS devices suitable for IoT applications.

关键词： Accelerometers Three-dimensional printing Three-dimensional displays Sensors Capacitance Fabrication programmable logic arrays Conductive composite material integrated 3D printing machine learning sensor

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OPTIMAL STATE CHAINS AND STATE CODES IN FINITE STATE MACHINES

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第2期8卷 153-170页

作者： AMANN, R BAITINGER, UG UNIV KARLSRUHE INST TECH INFORMAT PROCDEPT ELECT ENGND-7500 KARLSRUHEFED REP GER

A method is presented for the synthesis of optimal regular digital control structures in VLSI circuits. The controllers are modeled as finite-state machines and implemented using counter-based programmable-logic-array structures. Although those structures have already been used in the past, their complete automated design was impossible, due to missing state-assignment algorithms. The state-assignment algorithms presented to close this gap optimize the required silicon area of the controllers. They are divided into two steps: state-chain calculation and state-chain coding. In state-chain calculation the internal states of a finite-state machine are ordered to maximally exploit the counter characteristics. In state-chain coding the internal states are coded so that the state sequences are maintained, while coding constraints are satisfied that permit a further minimization of the circuit.< >

关键词： Automata programmable logic arrays Circuit synthesis Very large scale integration Silicon Minimization Digital control Automatic control Design methodology logic design

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Controlling the stereostructure of non-planar ring to induce the transition from plastic to elastomer in poly(butylene adipate-co-1,4-cyclohexane dicarboxylate) and implement of polylactic acid toughness

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POLYMER ENGINEERING AND SCIENCE 2017年第12期57卷 1277-1284页

作者： Qiu, Jia Liu, Fei Zhang, Junwu Chen, Jing Na, Haining Zhu, Jin Chinese Acad Sci Ningbo Key Lab Polymer Mat Ningbo Inst Mat Technol & Engn Ningbo 315201 Zhejiang Peoples R China

The controllable polyesters with high overall performance are obtained by tuning the stereostructure of 1,4-cyclohexylene ring moieties (CHRMs) in poly(butylene adipate-co-1,4-cyclohexanedicarboxylate) (PBAC). After increasing the number of irregular cis-CHRMs in the polyester, PBAC can transform from semicrystalline polymer to amorphous one. PBAC with 58% cis-CHRMs starts to exhibit good elasticity with shape recovery of 60% at 250% deformation, indicating the transition from plastic to thermoplastic elastomer. Through blending with polylactic acid (PLA), the elastic PBAC greatly enhances the impact strength of PLA to 7.5 kJ/m(2). While the tensile elongation at break is dramatically improved to 161% with the addition of plastic PBAC. The mechanism related to the stereostructure of non-planar ring of PBAC on the properties of PLA is also analyzed. Therefore, this research suggests a particular way to build non-planar ring contained polyesters to modify PLA with high toughness. POLYM. ENG. SCI., 57:1277-1284, 2017. (c) 2017 Society of Plastics Engineers

关键词： Impact strengths dicarboxylate RINGS TOUGHNESS rings Plastics programmable logic arrays elastic bodies Annulus Polyesters Ring device polybutene Elongation at break poly(lactic acid)

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A GALLIUM-ARSENIDE CONFIGURABLE CELL ARRAY USING BUFFERED FET logic

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1984年第5期19卷 728-738页

作者： DEMING, RN ZUCCA, R VAHRENKAMP, RP HOU, LD NAUSED, BA GILBERT, BK MAYO FDN SPECIAL PURPOSE PROC DEV GRPROCHESTERMN 55905 ROCKWELL INT CORP CTR MICROELECTR RES & DEVTHOUSAND OAKSCA 91360

A GaAs configurable cell array has been fabricated using 1-/spl mu/m gate MESFETs on 3-in GaAs substrates using a planar fabrication technique. Depletion-mode MESFETs configured in buffered FET logic structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 fJ and 460 fJ. A 306-cell array (equivalent to approximately 430 NOR gates) occupying a chip area of 2.0/spl times/2.8 mm was fabricated. A 5/spl times/5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns and a power dissipation ranging from 337 to 722 mW, corresponding to a cell power of 1.30-2.79 mW/cell.

关键词： logic arrays Gallium arsenide FETs MESFETs Routing programmable logic arrays Fabrication logic devices logic functions Velocity measurement

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A Novel Parallel In-Memory logic Array Based on programmable Diodes

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2024年 12卷 738-744页

作者： Ye, Jiabao Zhu, Junyu Cao, Jifang Bi, Haoxiong Ding, Yong Chen, Bing Zhejiang Univ Sch Integrated Circuits Hangzhou 310027 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Xidian Univ Hangzhou Inst Technol Hangzhou 311231 Peoples R China

Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode-a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.

关键词： logic Semiconductor diodes Integrated circuit modeling logic gates Voltage control programmable logic arrays Computational modeling CIM 5KB logic array parallel 8-bit full adder programmable diode

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