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COMPARISON OF PROBABILISTIC PRODUCTION COST SIMULATION METHODS

IEEE TRANSACTIONS ON POWER SYSTEMS 1989年第4期4卷 1326-1334页

作者： LIN, M BREIPOHL, A LEE, F University of Oklahama Norman OK USA

The authors present the results of an investigation of the relative computational speeds and solution qualities of six different probabilistic production cost simulation methods for power systems. The six methods are: the piecewise linear approximation (PLA), segmentation, equivalent energy function (EEF), cumulant, mixture of normal approximation (MONA), and fast Fourier transform (FFT) methods. For energy calculations, considering both speed and accuracy, it is concluded that if accuracy is paramount then the EEF method with the MW interval chosen to be the maximum common divisor of the block capacities is preferred. If speed is paramount, then either MONA or cumulants is preferred.< >

关键词： Production Costs Random variables Computational modeling Character generation Piecewise linear approximation Fourier transforms Equations Art programmable logic arrays

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THE CNN UNIVERSAL MACHINE - AN ANAlogic ARRAY COMPUTER

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1993年第3期40卷 163-173页

作者： ROSKA, T CHUA, LO UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720 UNIV CALIF BERKELEY ELECTR RES LABBERKELEYCA 94720

In this paper a new invention, the CNN universal machine and supercomputer, is presented. This is the first algorithmically programmable analog array computer having real time and supercomputer power on a single chip. First, the CNN universal machine is described emphasizing its programmability as well as global and distributed analog memory and logic, high throughput via electromagnetic waves, and complex cells that may be used also for simulating a broad class of PDE's. Its implementation, the CNN universal chip is also described along with its use as a multichip supercomputer. Other types of hardware implementations are also briefly discussed. Details of the algorithmic aspects of the new type of analogic 1 algorithms, as well as the analogic software (language, compiler, machine code, etc.) are explained next, along with a brief description of the available CNN workstation for implementing and simulating these new concepts. Finally, a broad range of applications is reviewed, including neuromorphic computing, ''programmable physics,'' ''programmable chemistry,'' and ''programmable bionics.''

关键词： Cellular neural networks Turing machines Supercomputers Computational modeling Software algorithms programmable logic arrays Analog computers Analog memory Throughput Electromagnetic scattering

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Physical Layer Authentication for Non-Coherent Massive SIMO-Enabled Industrial IoT Communications

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2020年 15卷 3722-3733页

作者： Gu, Zhifang Chen, He Xu, Pingping Li, Yonghui Vucetic, Branka Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Peoples R China Chinese Univ Hong Kong Dept Informat Engn Hong Kong Peoples R China Univ Sydney Sch Elect & Informat Engn Camperdown NSW 2006 Australia

Achieving ultra-reliable, low-latency and secure communications is essential for realizing the industrial Internet of Things (IIoT). Non-coherent massive multiple-input multiple-output (MIMO) is one of promising techniques to fulfill ultra-reliable and low-latency requirements. In addition, physical layer authentication (PLA) technology is particularly suitable for secure IIoT communications thanks to its low-latency attribute. A PLA method for non-coherent massive single-input multiple-output (SIMO) IIoT communication systems is proposed in this paper. This method realizes PLA by embedding an authentication signal (tag) into a message signal, referred to as "message-based tag embedding". It is different from traditional PLA methods utilizing uniform power tags. We design the optimal tag embedding and optimize the power allocation between the message and tag signals to characterize the trade-off between the message and tag error performance. Numerical results show that the proposed message-based tag embedding PLA method is more accurate than the traditional uniform tag embedding method which has an unavoidable tag error floor close to 10%.

关键词： programmable logic arrays Authentication Physical layer Wireless communication Message authentication Massive SIMO non-coherent communication physical layer authentication industrial Internet of Things

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DESIGN AND SYNTHESIS OF SELF-CHECKING VLSI CIRCUITS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1993年第6期12卷 878-887页

作者： JHA, NK WANG, SJ Department of Electrical Engineering Princeton University Princeton NJ USA

Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur;thus, data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits. In this paper, we explore methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers. The area overhead for all proposed design alternatives is studied in detail.

关键词： Circuit synthesis Very large scale integration Circuit faults programmable logic arrays Electrical fault detection Fault detection Integrated circuit interconnections Circuits and systems Contamination Voltage

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Blends of polylactic acid with thermoplastic copolyester elastomer: Effect of functionalized terpolymer type on reactive toughening

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POLYMER ENGINEERING AND SCIENCE 2018年第3期58卷 280-290页

作者： Nagarajan, Vidhya Mohanty, Amar K. Misra, Manjusri Univ Guelph Sch Engn Guelph ON N1G 2W1 Canada Univ Guelph Dept Plant Agr Bioprod Discovery & Dev Ctr Guelph ON N1G 2W1 Canada

This study is an attempt to explore the effectiveness of thermoplastic copolyester elastomer (TPCE) as a toughening agent for improving the impact strength of PLA. Biobased Hytrel((R)) thermoplastic copolyester of polyether glycol and polybutylene terephthalate was selected as the TPCE of choice for this study. Blends of PLA/Hytrel at varying weight ratios were prepared using extrusion followed by injection molding technique. Optimal synergies of two polymers were found in the PLA/Hytrel (70/30) blend, showing impact strength of 234 J/m, a sixfold increase compared to neat PLA. In order to obtain further enhancement in toughness, different functionalized terpolymers were added to accomplish reactive compatibilization. A series of functionalized terpolymers, ethylene methyle acrylate-glycidyl methacrylate (EMA-GMA), ethylene butyl acrylate-glycidyl methacrylate (EBA-GMA), ethylene methyl acrylate-maleic anhydride (EMA-MaH), and ethylene butyl acrylate-maleic anhydride (EBA-MaH) were selected. Comparing PLA ternary blends with different terpolymers, GMA containing terpolymers showed better impact toughness compared to MaH terpolymer blends. Unique fracture surface morphology showing debonding cavitation and massive shear yielding in the ternary blends containing EMA-GMA resulted in super toughened blends. Highest zero shear viscosity and storage modulus was also observed for ternary blends with EMA-GMA. Under the processing conditions and blend ratio investigated, EMA-GMA showed better efficiency in improving the toughness of the PLA blends. POLYM. ENG. SCI., 58:280-290, 2018. (c) 2017 Society of Plastics Engineers

关键词： poly(lactic acid) SHEAR YIELDING TERNARY BLEND Impact strengths Terpolymers Polyethylene Glycols Thermoplasts programmable logic arrays Toughening polybutylene terephthalate elastic bodies ethylene Blends IMPACT TOUGHNESS

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AN ALGORITHM FOR MULTIPLE OUTPUT MINIMIZATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第9期8卷 1007-1013页

作者： GURUNATH, B BISWAS, NN INDIAN INST SCI DEPT ELECT COMM ENGN BANGALORE 560012 KARNATAKA INDIA UNIV SW LOUISIANA CTR ADV COMP STUDIES LAFAYETTE LA 70504 USA

A computer-aided design procedure for the minimization of multiple-output Boolean functions as encountered in the synthesis of VLSI logic circuits is presented. A fast technique for the determination of essential prime cubes without generating all the prime cubes is among the salient features of the algorithm. A new class of selective prime cubes called valid selective prime cubes is described. This class of prime cubes has proved to be a very powerful tool inasmuch as it guides the algorithm to the minimal set of selective prime cubes while encountering either an independent chain or an interconnected chain of cyclic prime cubes. In many cases, this avoids branching, which is computationally an expensive operation. The algorithm does not generate either the complement or all the prime cubes of the functions. Therefore, it is well suited to minimizing functions with a large complement size and/or a very high number of prime cubes. The algorithm has been implemented in Pascal and evaluated using a large number of programmable logic arrays (PLAs) including those of the Berkeley PLA test set. Results of comparison with ESPRESSO II and McBOOLE indicate that the program produces absolute minimal solutions in most of the cases and near-minimal solutions in a few others.< >

关键词： Minimization methods programmable logic arrays Very large scale integration Design automation Boolean functions logic circuits logic testing Message-oriented middleware Frequency Iterative algorithms

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Instance-Specific Semantic Augmentation for Long-Tailed Image Classification

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IEEE TRANSACTIONS ON IMAGE PROCESSING 2024年 33卷 2544-2557页

作者： Chen, Jiahao Su, Bing Renmin Univ China Gaoling Sch Artificial Intelligence Beijing Key Lab Big Data Management & Anal Methods Beijing 100872 Peoples R China

Recent long-tailed classification methods generally adopt the two-stage pipeline and focus on learning the classifier to tackle the imbalanced data in the second stage via re-sampling or re-weighting, but the classifier is easily prone to overconfidence in head classes. Data augmentation is a natural way to tackle this issue. Existing augmentation methods either perform low-level transformations or apply the same semantic transformation for all instances. However, meaningful augmentations for different instances should be different. In this paper, we propose feature-level augmentation (FLA) and pixel-level augmentation (PLA) learning methods for long-tailed image classification. In the first stage, the feature space is learned from the original imbalanced data. In the second stage, we model the semantic within-class transformation range for each instance by a specific Gaussian distribution and design a semantic transformation generator (STG) to predict the distribution from the instance itself. We train STG by constructing ground-truth distributions for instances of head classes in the feature space. In the third stage, for FLA, we generate instance-specific transformations by STG to obtain feature augmentations of tail classes for fine-tuning the classifier. For PLA, we use STG to guide pixel-level augmentations for fine-tuning the backbone. The proposed augmentation strategy can be combined with different existing long-tail classification methods. Extensive experiments on five imbalanced datasets show the effectiveness of our method.

关键词： Tail Semantics Head programmable logic arrays Training Image classification Reliability Long-tailed distribution image classification instance augmentation imbalanced data

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Symbolic two-level minimization

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第7期16卷 692-708页

作者： Villa, T Saldanha, A Brayton, RK Sangiovanni-Vincentelli, AL PARADES I-00186 Rome Italy Cadence Berkeley Labs Berkeley CA 94704 USA Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

In this paper, we present a symbolic minimization procedure to obtain optimal two-level implementations of finite-state machines. Encoding based on symbolic minimization consists of optimizing the symbolic representation, and then transforming the optimized symbolic description into a compatible two-valued representation by satisfying encoding constraints (bitwise logic relations) imposed on the binary codes that replace the symbols, Our symbolic minimization procedure captures the sharing of product terms due to ORing effects in the output part of a two-level implementation of the symbolic cover, Face, dominance, and disjunctive constraints are generated, Product terms are accepted in a symbolic minimized cover only when they induce compatible encoding constraints, At the end, a set of codes that satisfy all constraints Is computed, The quality of this synthesis procedure is shown by the fact that the cardinality of the cover obtained by symbolic minimization and of the cover obtained by replacing the codes in the initial cover and then minimizing it with ESPRESSO are very close, Experiments show that in some cases, our procedure improves on the best results of state-of-art tools.

关键词： Encoding Minimization methods logic functions Constraint optimization programmable logic arrays Binary codes Cost function Field programmable gate arrays Energy consumption

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SINGLE CHIP IMPLEMENTATION OF THE LEVINSON ALGORITHM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年第5期20卷 1072-1079页

作者： KONSTANTINIDES, K TYREE, VC YAO, K UNIV CALIF LOS ANGELES DEPT COMP SCILOS ANGELESCA 90024 UNIV CALIF LOS ANGELES DEPT ELECT ENGNLOS ANGELESCA 90024

The design, implementation, and testing procedure are presented for a single chip implementation of the Levinson algorithm. This algorithm provides an iterative procedure for the solution of certain systems of linear equations and is used in many basic problems in communications and signal processing. This chip consists of a 1200-bit RAM memory, a divider based on the nonrestoring division algorithm, a recorder-based multiplier suitable for pipelined operations, and a controller that consists of two PLAs and six address registers. Modifications of the algorithm permit the parallel use of both the multiplier and the divider. The design is done in 4-/spl mu/m NMOS technology, and 12-bit-long operants in two's complement are used. By using a 5-MHz two-phase clock, the chip can compute 20 iterations of the algorithm in approximately 675 /spl mu/s. Application to lattice filtering in linear data channel equilization is considered. Off-line testing of the chip can be done effectively with minimum additional hardware through separate data and control buses.

关键词： Signal processing algorithms Iterative algorithms Testing Algorithm design and analysis Equations Read-write memory Random access memory Communication system control programmable logic arrays Registers

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Design, Fabrication, and Locomotion Analysis of an Untethered Miniature Soft Quadruped, SQuad

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IEEE ROBOTICS AND AUTOMATION LETTERS 2020年第3期5卷 3854-3860页

作者： Kalin, Mert Ali Ihsan Aygul, Cem Turkmen, Altay Kwiczak-Yigitbasi, Joanna Baytekin, Bilge Ozcan, Onur Bilkent Univ Dept Mech Engn Ankara 06800 Turkey Bilkent Univ Dept Chem Ankara 06800 Turkey

The conventional robotics, which involves utilization of robots made out of hard materials like metals and hard plastics, has helped humankind automate many different sorts of labor and such robots have been assisting the humans in various tasks. Nevertheless, some applications require very delicate interactions and adaptability of the robots to unstructured elements and obstacles;which can only be provided by softness. The miniature and untethered robot in this work is fully made out of soft structural materials and uses a flexible circuit board. Only the electronic components, actuators and several little connection parts are hard. Its soft legs, body, and circuit enables it to overcome obstacles that conventional hard miniature robots tend to be stopped by. For the soft robot presented, walking and obstacle climbing experiments were done and pitch angle, roll angle, robot's centroid position and stiffness analyses were conducted. Additionally, three other robots are fabricated in hard body - hard leg, hard body - soft leg, and soft body - hard leg configurations and the effects of body and leg compliance on the locomotion performance are investigated. The results show that a soft body - soft leg robot configuration can scale an obstacle 1.44 times its body height whereas the hard bodied and hard legged robot can only go over 0.88 times its body height. The results also indicate that the softness of the body effects the scalable obstacle height more than the softness of the legs at this length scale.

关键词： Legged locomotion Soft robotics DC motors programmable logic arrays Connectors Robot sensing systems Soft robot materials and design soft robot applications legged robots

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