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Design, Fabrication, and Locomotion Analysis of an Untethered Miniature Soft Quadruped, SQuad

IEEE ROBOTICS AND AUTOMATION LETTERS 2020年第3期5卷 3854-3860页

作者： Kalin, Mert Ali Ihsan Aygul, Cem Turkmen, Altay Kwiczak-Yigitbasi, Joanna Baytekin, Bilge Ozcan, Onur Bilkent Univ Dept Mech Engn Ankara 06800 Turkey Bilkent Univ Dept Chem Ankara 06800 Turkey

The conventional robotics, which involves utilization of robots made out of hard materials like metals and hard plastics, has helped humankind automate many different sorts of labor and such robots have been assisting the humans in various tasks. Nevertheless, some applications require very delicate interactions and adaptability of the robots to unstructured elements and obstacles;which can only be provided by softness. The miniature and untethered robot in this work is fully made out of soft structural materials and uses a flexible circuit board. Only the electronic components, actuators and several little connection parts are hard. Its soft legs, body, and circuit enables it to overcome obstacles that conventional hard miniature robots tend to be stopped by. For the soft robot presented, walking and obstacle climbing experiments were done and pitch angle, roll angle, robot's centroid position and stiffness analyses were conducted. Additionally, three other robots are fabricated in hard body - hard leg, hard body - soft leg, and soft body - hard leg configurations and the effects of body and leg compliance on the locomotion performance are investigated. The results show that a soft body - soft leg robot configuration can scale an obstacle 1.44 times its body height whereas the hard bodied and hard legged robot can only go over 0.88 times its body height. The results also indicate that the softness of the body effects the scalable obstacle height more than the softness of the legs at this length scale.

关键词： Legged locomotion Soft robotics DC motors programmable logic arrays Connectors Robot sensing systems Soft robot materials and design soft robot applications legged robots

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SINGLE CHIP IMPLEMENTATION OF THE LEVINSON ALGORITHM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年第5期20卷 1072-1079页

作者： KONSTANTINIDES, K TYREE, VC YAO, K UNIV CALIF LOS ANGELES DEPT COMP SCILOS ANGELESCA 90024 UNIV CALIF LOS ANGELES DEPT ELECT ENGNLOS ANGELESCA 90024

The design, implementation, and testing procedure are presented for a single chip implementation of the Levinson algorithm. This algorithm provides an iterative procedure for the solution of certain systems of linear equations and is used in many basic problems in communications and signal processing. This chip consists of a 1200-bit RAM memory, a divider based on the nonrestoring division algorithm, a recorder-based multiplier suitable for pipelined operations, and a controller that consists of two PLAs and six address registers. Modifications of the algorithm permit the parallel use of both the multiplier and the divider. The design is done in 4-/spl mu/m NMOS technology, and 12-bit-long operants in two's complement are used. By using a 5-MHz two-phase clock, the chip can compute 20 iterations of the algorithm in approximately 675 /spl mu/s. Application to lattice filtering in linear data channel equilization is considered. Off-line testing of the chip can be done effectively with minimum additional hardware through separate data and control buses.

关键词： Signal processing algorithms Iterative algorithms Testing Algorithm design and analysis Equations Read-write memory Random access memory Communication system control programmable logic arrays Registers

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Transformational DT-CNN design from morphological specifications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 1998年第9期45卷 879-888页

作者： ter Brugge, MH Nijhuis, JAG Spaanenburg, L Univ Groningen Dept Comp Sci NL-9700 AV Groningen Netherlands

Morphology provides the algebraic means to specify operations on images. Discrete-time cellular neural networks (DT-CNN's) mechanize the execution of operations on images, The paper first shows the equivalence between morphological functions and DT-CNN's, Then, the argument is extended to the synthesis of optimal DT-CNN structures from complex morphological expressions. It is shown that morphological specifications may be freely derived, to be subsequently transformed and adopted to the needs of a specific target technology. This process of technology mapping can be automated along the well-trodden path in CAD for microelectronics.

关键词： Cellular neural networks Image processing programmable logic arrays Morphology Design optimization Differential equations Algorithm design and analysis Image reconstruction Network synthesis Microelectronics

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SUBOPTIMAL SOLUTION FOR PLA MULTIPLE COLUMN FOLDING

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COMPUTER-AIDED DESIGN 1990年第8期22卷 515-526页

作者： LUCCIO, F PINOTTI, MC CNR IST ELABORAZ INFORMAZI-56100 PISAITALY

The paper studies the problem of multiple column folding in the design of compact PLAs of m rows and n columns. A set of theoretical results leads to the construction of a heuristic algorithm which builds the folded P... 详细信息

关键词： multiple column folding heuristic algorithm programmable logic arrays

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Functional test generation for synchronous sequential circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1996年第7期15卷 831-843页

作者： Srinivas, MK Jacob, J Agrawal, VD INDIAN INST SCI DEPT ELECT COMMUN ENGN BANGALORE 560012 KARNATAKA INDIA

We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLA's are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator, Results on a broad class of small to large synthesis benchmark FSM's from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate Level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests.

关键词： Circuit testing Sequential analysis Synchronous generators Sequential circuits Circuit faults programmable logic arrays logic testing Combinational circuits Benchmark testing Automata

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QoS adaptive transports: Delivering scalable media to the desktop

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IEEE NETWORK 1997年第2期11卷 18-27页

作者： Campbell, AT Coulson, G UNIV LANCASTER LANCASTER LA1 4YWENGLAND

By trading off temporal and spatial quality with available bandwidth, or manipulating the playout time of continuous media in response to variation in delay, audio and video flows can be made to adapt to fluctuating network conditions with minimal perceptual distortion. In this article the authors describe the implementation of an adaptive transport system that incorporates a QoS-oriented API and a range of QoS mechanisms that best assist multimedia applications in adapting to fluctuations in the delivered network QoS. The system, which is an instantiation of the transport and network layers of a QoS architecture, is implemented in a multi-ATM switch network environment with Linux-based PC end systems and continuous media file servers. A performance evaluation of the system configured to support a video-on-demand application scenario is presented and discussed. A novel aspect of the system is the implementation of a ''QoS adaptation'' algorithm which allows applications to delegate to the transport system responsibility for augmenting or reducing the perceptual quality of video and audio flows when network resource availability increases or decreases, respectively.

关键词： Protocols Multimedia systems Jitter Monitoring Bandwidth Delay Fluctuations Switches Resource management programmable logic arrays

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THE DESIGN OF A FULLY INTEGRATED GRAPHICS SYSTEM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1988年第2期23卷 368-376页

作者： TORRANCE, RR SADLER, SP LAMOUREUX, JP LAMARCHE, J FRANK, DJ LEVEILLE, F Silicart Inc. Vaudreuil QUE Canada Bell Northern Research Limited Ottawa ONT Canada Silicart Inc. Vaudreuil Que. Canada

The architecture and design of a CMOS chip implementing a medium-resolution graphics system are described. The chip, requiring no external support logic, outputs analog RGB signals at a 40-MHz pixel rate and directly controls a bit-map video RAM (VRAM) memory array. Scan rates and display formats are completely programmable. Pixels stored in the 1 K*1 K bit map can be any of 16 colors taken from a 4096-color palette. The chip can be directly interfaced to most common microprocessors. A 6.7-MIPS (million-instruction-per-second) internal reduced instruction set computer (RISC) CPU directly implements high-level graphics commands. The chip achieves a maximum draw speed of 10 million pixels/s. Designed in a Lisp machine environment, the 100000-transistor chip is implemented in 1.8- mu m CMOS and contains standard cells, RAM, ROM, a color table, and three four-bit current-steered digital-to-analog converters (DACs).< >

关键词： Graphics logic arrays Read-write memory CMOS logic circuits Random access memory programmable logic arrays Computer displays Color Microprocessors Computer aided instruction

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THE NEW UA1 CALORIMETER TRIGGER PROCESSOR

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1989年第1期36卷 364-369页

作者： BAIRD, SA BAINS, N CAMPBELL, D CAWTHRAW, M CHARLTON, D COUGHLAN, J EISENHANDLER, E ELLIS, N FENSOME, I FLYNN, P GALAGADERA, S GARVEY, J GRAYER, G GREGORY, J HALSALL, R JIMACK, MP JOVANOVIC, P KENYON, IR LANDON, M SHAH, TP STEPHENS, R UNIV LONDON QUEEN MARY COLL LONDON E1 4NSENGLAND RUTHERFORD APPLETON LAB DIDCOT OX11 0QXOXONENGLAND

The UA1 first level trigger processor (TP) is a fast digital machine with a highly parallel pipelined architecture of fast combinational and programmable transistor-transistor logic controlled by programmable microsequencers. The TP uses 100000 ICs (integrated circuits) housed in 18 crates each containing 21 FASTBUS-sized molecules. It is hardwired with a very high level of interconnection. The energy deposited in the upgraded calorimeter is digitized into 1700 bytes of input data every beam crossing (3.8 mu s). The processor selects in 1.5 mu s events for further processing (1 in 30000). The trigger has improved hadron jet rejection, achieved by requiring low-energy deposition around the electromagnetic cluster. A missing-transverse-energy trigger and a total-energy trigger have also been implemented.< >

关键词： Electrons Poles and towers Mesons Educational institutions Laboratories Architecture programmable logic arrays programmable logic devices programmable control Fastbus

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Multi-camera systems - Calibration and applications

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IEEE SIGNAL PROCESSING MAGAZINE 1999年第3期16卷 55-65页

作者： Pedersini, F Sarti, A Tubaro, S

In this article, we present some simple and effective techniques for accurately calibrating a multi-camera acquisition system. The proposed methods were proven to be capable of accurate results even when using very simple calibration target sets and low-cost imaging devices, such as standard TV-resolution cameras connected to commercial frame-grabbers. In fact, the performance of our calibration approach yielded results that were about the same as that of other traditional calibration methods based on large 3D target sets. The proposed calibration strategy is based on a multi-view multi-camera approach. This was based on the analysis of a number of views of a simple calibration target-set placed in different (unknown) positions. Furthermore, the method is based on a self-calibration approach, which can refine the a priori knowledge of the world coordinates of the targets (even when such information is very poor) while estimating the parameters of the camera model. Finally we proposed a method, to make the calibration technique adaptive through the analysis of natural scene features, allowing the camera parameters to hold accurate throughout the acquisition session in the presence of parameter drift.

关键词： Cameras Nonlinear distortion Calibration Layout Optical distortion Lenses Nonlinear optics Pixel Polynomials programmable logic arrays

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A 6K-GATE GAAS GATE ARRAY WITH A NEW LARGE-NOISE-MARGIN SLCF CIRCUIT

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第5期22卷 755-761页

作者： TERADA, T IKAWA, Y KAMEYAMA, A KAWAKYU, K SASAKI, T KITAURA, Y ISHIDA, K NISHIHORI, K TOYODA, N VLSI Research Center Toshiba Corporation Kawasaki Japan

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.

关键词： Gallium arsenide logic arrays Power dissipation Optical arrays programmable logic arrays FETs logic design logic circuits MESFET circuits Inverters

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