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Physical extruder foaming of poly(lactic acid)processing and foam properties

POLYMER ENGINEERING AND SCIENCE 2013年第5期53卷 941-949页

作者： Larsen, Age Neldin, Christoffer SINTEF Mat & Chem NO-0314 Oslo Norway Borealis AB SE-44486 Stenungsund Sweden

The article describes extrusion foaming of poly(lactic acid) (PLA) using carbon dioxide in the supercritical state as foaming agent emphasizing the steps required to establish a stable extrusion process. Low melt strength of PLA plays a role in optimizing processing conditions. The tests included PLA grades of different viscosity in addition to a chain extender. Processing at low temperature is possible due to the plasticizing effect of the CO2 on the PLA melt and a sufficiently low melt temperature is also a prerequisite in production of stable foams due to improved melt strength. Foams were characterized by density, cell structure, crystallinity, and mechanical properties in compression. Low density, microcellular foams with density down to 2030 kg/m3 were obtained for three different PLA grades. Varying die temperature and pressure drop rate we can explain observed abrupt drops in density with increasing CO2 content by the interplay between cell nucleation and gas diffusivity at given temperatures. An effect on melt strength similar to using a chain extender is achieved by lowering the melt temperature at the die. Observed variations in sample crystallinity do not correlate with foam density. The PLA foams have good energy absorption capability. POLYM. ENG. SCI., 2013. (c) 2012 Society of Plastics Engineers

关键词： poly(lactic acid) energy absorption ability Mechanical properties MELT STRENGTH extrusion process melting point programmable logic arrays Carbon Dioxide Foaming

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Burned data time series for Tropical Africa (1981-2000) with the daily tile NOAA/NASA Pathfinder AVHRR 8-km Land dataset

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INTERNATIONAL JOURNAL OF REMOTE SENSING 2006年第5-6期27卷 1119-1134页

作者： Moreno-Ruiz, JA Barón-Martinez, J Sagrado-Martínez, J Univ Almeria Dept Lenguajes & Computac Almeria 04120 Spain

The NOAA/NASA Pathfinder AVHRR 8-km Land (PAL) dataset provides an invaluable source of data for researching global changes on the Earth's surface due to its long time and spatial scales. However, because of errors, the original Global Daily PAL data (1981-1994) have been reprocessed into a tiled time series file configuration. Reprocessing involved calculating the correct solar zenith angles and relative azimuth angles, and re-extracting radiances from the original Channel I and 2 reflectance values. The high dependence of the burned area algorithm (BAA) with respect to reflectance channel uncertainty led us, as a first goal, to compare the two dataset releases to determine the magnitude of their differences and how burned area estimations could be affected by them: the new burned data estimations from the Tile PAL release are around 30% higher than those from the original one. The second goal was to present and briefly analyse the monthly burned time series (13S) for Tropical Africa for the period 19812000: stational indexes show that the burned pixel peaks in the time series for northern Tropical Africa appear in winter (from December to February), while ill southern Tropical Africa they are in summer (from July to September). Chronograms show a significant interannual seasonal variation in both (being more apparent in the southern region) possibly as a consequence of the influence of the El Nino Southern Oscillation (ENSO) phenomenon-induced Sea Surface Temperature (SST) anomalies in the Pacific Ocean (annual average SST-3.4 and delayed one year and a half BS anomalies were found in the period considered).

关键词： Data sources LRIT1 gene SHCBP1 gene Burns Pacific Ocean Azimuthal angle programmable logic arrays El Nino Southern Oscillation time series data Tile Time series Earth surface Africa tropical Dataset

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Preparation of biocompatible, biodegradable and sustainable polylactides catalyzed by aluminum complexes bearing unsymmetrical dinaphthalene-imine derivatives via ring-opening polymerization of lactides

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CATALYSIS SCIENCE & TECHNOLOGY 2015年第9期5卷 4644-4652页

作者： Gao, Bo Li, Dongni Li, Xiang Duan, Ranlong Pang, Xuan Cui, Yuan Duan, Qian Chen, Xuesi Chinese Acad Sci Changchun Inst Appl Chem Key Lab Polymer Ecomat Changchun 130022 Peoples R China Changchun Univ Sci & Technol Sch Mat Sci & Engn Changchun 130022 Peoples R China

A number of half-salen aluminum complexes bearing unsymmetrical [ONN]-type ligands were prepared from tridentate dinaphthalene-imine derivatives. These complexes were characterized by H-1 and C-13 NMR spectroscopy, elemental analysis and single crystal X-ray diffraction analysis. These complexes were employed for rac-lactide and L-lactide polymerization. Upon activation with isopropanol, complex (S)-B-6 (R-1 = R-2 = R-4 = H;R-3 = F) showed the highest activity (a monomer conversion of 94.6%) amid these aluminum complexes for the ring-opening polymerization of L-lactide;and complex (S)-B-2 (R-1 = R-2 = R-3 = H;R-4 = Bu-t) showed the highest stereoselectivity for the ring-opening polymerization of rac-lactide, obtaining a polylactide (PLA) with a Pm of 0.69. The polymerization kinetics utilizing (S)-B-6 as a catalyst were researched in detail. The data on the polymerization kinetics revealed that the rate of polymerization was first-order with respect to the monomer and the catalyst. There was a linear relationship between the L-lactide conversion and the number-average molecular weight of PLA.

关键词： programmable logic arrays Bearings Ring opening polymerization ALUMINIUM COMPLEXES Polylactides monomers Polymerization aluminium Polymerization kinetics non-symmetric

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CONCURRENT ERROR-DETECTION IN HIGHLY STRUCTURED logic-arrays

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第4期22卷 583-594页

作者： FUCHS, WK CHEN, CYR ABRAHAM, JA Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.

关键词： logic arrays Fault detection Circuit faults programmable logic arrays logic devices Encoding Very large scale integration Testing Decoding Read only memory

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A STATISTICAL-ANALYSIS OF PLA FOLDING

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第1期5卷 39-51页

作者： MAKARENKO, DD TARTAR, J Department of Computing Science University of Alberta Edmonton AB Canada

Current understanding of the PLA folding problem is limited to simple empirical evidence from studies of heuristic methods. This paper presents a theoretical approach through an analytical and statistical analysis. The problem is first mapped into a set theoretic model. Using a random selection heuristic as a basis, a probability density function (PDF) is derived for the expected number of folds under a set of simplifying assumptions. This PDF is derived in terms of the three fundamental properties of a PLA, r the number of rows, c the number of columns, and d the density. Empirical results obtained from folding thousands of randomly generated PLA's verify the accuracy of the derived probability density function. A technique is developed whereby the PDF can also be used to predict the size of optimal folding sets. A new folding heuristic is introduced which is shown to perform better than other heuristic algorithms in the literature, when applied to a set of randomly generated PLA's. This is the first folding heuristic to have an analytical basis for its expected results, as derived from the PDF function.

关键词： Statistical analysis programmable logic arrays Probability density function logic design Heuristic algorithms Very large scale integration logic circuits Process design Automatic control

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Thermal Pretreatment of Kudzu Biomass (Pueraria lobata) as Filler in Cost-Effective PLA Biocomposite Fabrication Process

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POLYMER ENGINEERING AND SCIENCE 2015年第2期55卷 340-348页

作者： Salak, Feridoun Uemura, Satoshi Sugimoto, Kiyotoshi Nara Prefectural Govt Nara Prefecture Inst Ind Dev Life Mat Grp Nara 6308031 Japan

This article aims on the fabrication of cost-effective polylactic acid (PLA) biocomposites using kudzu biomass derivatives as new filler. In this way, it has been realized that pretreatment of the filler was an essential requirement. We demonstrated thermal pyrolysis process that targeted to extraction and isolation of all extractable and unnecessary compounds such as intracellular water and bio-oil from the biomass. Also, to further improve the compatibility of the filler with PLA, noncatalytic thermal esterification reactions of kudzu after thermal pyrolysis (called char) were carried out as second pretreatment stage in the presence of phthalic anhydride. Kudzu derivatives obtained from either first or second pretreatment reactions were melt-blended with PLA in various rates. The blends were then compression molded into dumbbell specimens. Physicomechanical properties of the prepared biocomposites were evaluated using several analytical techniques. It was found that biocomposites containing treated biomass had higher values of physicomechanical properties than untreated ones. The final rate of filler to PLA with acceptable properties was set up to 50%. Obviously, the cost of PLA can be reduced using higher rates of low-cost filler on a finished-product basis. Extracted valuable compounds from biomass via thermal pyrolysis could be another benefit of the process. POLYM. ENG. SCI., 55:340-348, 2015. (c) 2014 Society of Plastics Engineers

关键词： programmable logic arrays Fillers Biomass Kudzu BIOCOMPOSITE pyrolysis

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THE EFFICIENT IMPLEMENTATION AND ANALYSIS OF A HYBRID NUMBER SYSTEM PROCESSOR

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1993年第6期40卷 382-392页

作者： LAI, FS IBM Thomas J. Watson Research Center Yorktown Heights NY USA

A hybrid number system processor designed with the anti-logarithm PLA is described. In the hybrid number system, a linear interpolation is used in order to make accurate conversions between FLP and LNS numbers. Originally, a multiplier was used to do the interpolation. In this paper, the anti-logarithm PLA is shown to have smaller silicon area, comparable overall performance, and structured design. The basic arithmetic operations and processor architecture are explained for performing addition, subtraction, multiplication, division, and square root. The conversion errors are analyzed mathematically. The Taylor series approximation is used as the framework for analysis of the conversion errors of logarithm, anti-logarithm, multiplication/division, and addition/subtraction. The analyses indicate that the Taylor series truncation results in very small error when the ROM size is properly chosen for the desired precision. Consequently, the finite width truncation becomes the major source of conversion errors.

关键词： programmable logic arrays Interpolation Read only memory Silicon Arithmetic Error analysis Taylor series Digital signal processing logic design Process design

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RADIX-4 SQUARE ROOT WITHOUT INITIAL PLA

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IEEE TRANSACTIONS ON COMPUTERS 1990年第8期39卷 1016-1024页

作者： ERCEGOVAC, MD LANG, T Dept. of Comput. Sci. California Univ. Los Angeles CA USA

A systematic derivation of a radix-4 square-root algorithm using redundant residual and result is presented. Unlike other similar schemes it does not use a table lookup or PLA for the initial step, resulting in a simpler implementation without any time penalty. The scheme can be integrated with division and incorporates an on-the-fly conversion and rounding of the result, thus eliminating a carry-propagate step to obtain the final result. The result-digit selection uses 3 bits of the result and 7 bits of the estimate of the residual

关键词： ROT Scheme Table lookup programmable logic arrays 3-bit Time penalty rounding RESIDUAL final

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HI-MNOS II TECHNOLOGY FOR A 64-KBIT BYTE-ERASABLE 5-V-ONLY EEPROM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1985年第1期20卷 144-151页

作者： YATSUDA, Y NABETANI, S UCHIDA, K MINAMI, SI TERASAWA, M HAGIWARA, T KATTO, H YASUI, T HITACHI LTD MUSASHI WORKSKODAIRATOKYO 187JAPAN HITACHI MICROCOMP ENGN LTD KODAIRA 187JAPAN

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.

关键词： EPROM Switching circuits Low voltage programmable logic arrays DC generators Light emitting diodes logic design logic programming logic circuits Writing

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LEXICOGRAPHICAL EXPRESSIONS OF BOOLEAN FUNCTIONS WITH APPLICATION TO MULTILEVEL SYNTHESIS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1993年第11期12卷 1642-1654页

作者： SAUCIER, G FRON, J ABOUZEID, P GRENOBLE CSI INST NATL POLYTECHF-38031 GRENOBLEFRANCE

This paper proposes a new type of expression for Boolean functions called lexicographical expressions. The basic idea is to impose an input ordering for factoring logical expressions. Several algebraic properties are presented and relations with classical algebraic theory are established. The main result is that all elementary factorizations defined by (Cokernel, Kernel) pairs ''compatible'' with an input order are all ''algebraically compatible,'' i.e., are all parts of a single factorization of the function. Thus for a given input order a unique factorization is defined. This leads to fast division procedures. Basic techniques for obtaining lexicographical factorizations are presented. First, a precedence matrix and an updating procedure are defined and used later to select an input order and a corresponding compatible factorization. Second, a factorization technique respecting a fixed order is detailed. This method is then applied to multi-level synthesis using standard cells which was the original motivation of this work. The goal is to reduce wiring complexity. A lexicographical factorization leads to a wiring area reduction due to the structuring of the logic into layers in which the inputs enter the layout in the order given by the factorization. Experimental results comparing this approach to classical ones are given. These results include routing ratio measurements, routing structure observation, global area measurement and critical path estimation. All these results are analyzed after place and route, using an industrial tool (COMPASS Design Automation tool).

关键词： Boolean functions Wiring Routing Area measurement logic functions Design automation programmable logic arrays Input variables Kernel Circuits

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