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检索条件"主题词=Programmable Logic Arrays"
4433 条 记 录,以下是261-270 订阅
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Electrospun PLA: PCL composites embedded with unmodified and 3-aminopropyltriethoxysilane (ASP) modified halloysite nanotubes (HNT)
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APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING 2013年 第2期110卷 433-442页
作者: Haroosh, Hazim J. Dong, Yu Chaudhary, Deeptangshu S. Ingram, Gordon D. Yusa, Shin-ichi Curtin Univ Technol Dept Chem Engn Perth WA 6845 Australia Curtin Univ Technol Dept Mech Engn Perth WA 6845 Australia Univ Hyogo Dept Mat Sci & Chem Himeji Hyogo 6712280 Japan
Electrospinning is a simple and versatile fiber synthesis technique in which a high-voltage electric field is applied to a stream of polymer melt or polymer solution, resulting in the formation of continuous micro/nan... 详细信息
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Designing fault-tolerant techniques for SRAM-based FPGAs
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IEEE DESIGN & TEST OF COMPUTERS 2004年 第6期21卷 552-562页
作者: Kastensmidt, FGD Neuberger, G Hentschke, RF Carro, L Reis, R Univ Fed Rio Grande do Sul BR-90046900 Porto Alegre RS Brazil
FPAs have become prevalent in critical applications in which transient faults can seriously affect the circuits operation. This article presents a fault tolerance technique for transient and permanent faults in SRAM-b... 详细信息
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A KNOWLEDGE-BASED SYSTEM FOR DESIGNING TESTABLE VLSI CHIPS
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IEEE DESIGN & TEST OF COMPUTERS 1985年 第4期2卷 56-68页
作者: ABADIR, MS BREUER, MA University of Southern California
The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designing more easily tested circuits have evolved over the years, with particular emphasis on built-in ... 详细信息
来源: 评论
Tailoring the mechanical and thermal properties of polylactic acid-based bionanocomposite films using halloysite nanotubes and polyethylene glycol by solvent casting process
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JOURNAL OF MATERIALS SCIENCE 2019年 第12期54卷 8971-8983页
作者: Sharma, Swati Singh, Anshu Anjali Majumdar, Abhijit Butola, Bhupendra Singh Indian Inst Technol Delhi Dept Text Technol New Delhi 110016 India
The inherent brittleness of PLA is a major challenge for its use in various applications. In this study, the effect of incorporation of halloysite nanotube (HNT) and polyethylene glycol (PEG) on mechanical and thermal... 详细信息
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A programmable logic ARRAY SUITABLE FOR USE IN DIGITAL SYSTEM-DESIGN LABORATORIES
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IEEE TRANSACTIONS ON EDUCATION 1992年 第4期35卷 338-350页
作者: ABE, K OMORI, T NARAOKA, M HITACHI LTD KANAGAWA WORKSRISC DEVKANAGAWA 257JAPAN
A specially designed programmable logic array (PIA) suitable for use in digital system design laboratories for undergraduates is presented. Rewriting the PIA is done just by transfering the new codes;no explicit erasi... 详细信息
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Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs
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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2013年 第1期12卷 40-50页
作者: Gaillardon, Pierre-Emmanuel Sacchetto, Davide Beneventi, Giovanni Betti Ben Jamaa, M. Haykel Perniola, Luca Clermidy, Fabien O'Connor, Ian De Micheli, Giovanni Ecole Polytech Fed Lausanne Lab Syst Integrat CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Lab MicroElect Syst CH-1015 Lausanne Switzerland Commissariat Energie Atom & Energies Alternat F-38054 Grenoble France Ecole Cent Lyon F-69134 Ecully France Ecole Polytech Montreal PQ H3T 1J4 Canada
Emerging nonvolatile memories (ENVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access M... 详细信息
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3D Printing-Assisted Soft Capacitive Inclinometers for Simultaneous Monitoring of Tilt Angles and Directions
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IEEE ACCESS 2022年 10卷 31445-31454页
作者: Baek, Keuntae Bang, Joohyung Lee, Jihun Choi, Minyoung So, Hongyun Hanyang Univ Dept Mech Engn Seoul 04763 South Korea Hanyang Univ Inst Nano Sci & Technol Seoul 04763 South Korea
This study presents capacitive-type inclinometers composed of flexible polymer pillars and dome-shaped roof frames that were manufactured using the three-dimensional (3D) printing method. Polylactic acid (PLA) filamen... 详细信息
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SYNCHRONOUS logic SYNTHESIS - ALGORITHMS FOR CYCLE-TIME MINIMIZATION
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年 第1期10卷 63-73页
作者: DEMICHELI, G Comput. Syst. Lab. Stanford Univ. CA USA
A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance is presented. Previous... 详细信息
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A TECHNIQUE FOR PULL-UP TRANSISTOR FOLDING
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年 第8期7卷 887-896页
作者: LURSINSAP, C GAJSKI, DD UNIV CALIF IRVINE DEPT INFORMAT & COMP SCIIRVINECA 92717
The authors consider the constraint limiting multiple folding in programmable logic array (PLA) layouts imposed by the layout architecture which positions pull-up transistors on the boundary of the cell and uses anoth... 详细信息
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SPACE COMPACTION FOR MULTIPLE-OUTPUT CIRCUITS
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年 第10期7卷 1105-1113页
作者: SERRA, M MUZIO, JC VLSl Design and Test Group Department of Computer Science University of Victoria Victoria BC Canada
A counting signature for multiple-output circuits is introduced. It implements both time compaction and space compaction, such that a single signature is derived for all outputs, using a simple scheme with suitable bu... 详细信息
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