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Adduction of ammonium to polylactides to modify their dissociation behavior in collision-induced dissociation

RAPID COMMUNICATIONS IN MASS SPECTROMETRY 2018年第5期32卷 423-430页

作者： Chendo, Christophe Phan, Trang N. T. Rollet, Marion Gigmes, Didier Charles, Laurence Aix Marseille Univ CNRS Federat Sci Chim Marseille FR 1739 Marseille France Aix Marseille Univ CNRS ICR UMR 7273 Marseille France

RationaleThe goal of this work was to modify the dissociation pathways of polylactide (PLA) holding benzyl and hydroxyl terminations, in order to circumvent coincidence of product ions generated during collisional activation of sodiated chains, which prevented their reliable characterization. MethodsBenzyl-, hydroxyl-terminated PLAs were ionized as ammonium adducts in positive ion mode electrospray and subjected to collision-induced dissociation (CID). Tandem mass spectrometry (MS/MS) experiments were conducted in a quadrupole time-of-flight (QTOF) instrument for safe assignment of product ions based on their elemental composition derived from accurate mass measurements. ResultsAdduction of ammonium to PLAs was found to induce chain fragmentation via charge-assisted processes, in great contrast to the charge-remote mechanisms experienced by sodiated molecules. The main reaction produced ions containing the termination only, hence allowing straightforward end-group determination. Other minor pathways were studied in detail to establish dissociation rules for ammoniated PLAs. Some reactions were found to be end-group specific, highlighting the higher reactivity of ammonium than alkali ion adducts. ConclusionsChanging the usually employed sodium-cationizing agent to ammonium was shown to induce dramatic changes in the CID behavior of PLAs. This was a simple and efficient approach to address issues encountered for end-group analysis of the particular PLA studied here.

关键词： elemental composition Adduction programmable logic arrays charge injection devices collisional activation Polylactides ammonium Ions

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Designing fault-tolerant techniques for SRAM-based FPGAs

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IEEE DESIGN & TEST OF COMPUTERS 2004年第6期21卷 552-562页

作者： Kastensmidt, FGD Neuberger, G Hentschke, RF Carro, L Reis, R Univ Fed Rio Grande do Sul BR-90046900 Porto Alegre RS Brazil

FPAs have become prevalent in critical applications in which transient faults can seriously affect the circuits operation. This article presents a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CED) to provide a highly reliable circuit while maintaining hardware pin and power overheads far lower than with classic triple-modular-redundancy techniques.

关键词： Fault tolerance Field programmable gate arrays Circuit faults Routing Table lookup logic devices Integrated circuit interconnections Clocks Delay programmable logic arrays

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A KNOWLEDGE-BASED SYSTEM FOR DESIGNING TESTABLE VLSI CHIPS

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IEEE DESIGN & TEST OF COMPUTERS 1985年第4期2卷 56-68页

作者： ABADIR, MS BREUER, MA University of Southern California

The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designing more easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What has not evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodology provides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individual processing is described and a new concept-I-path-is used to transfer data from one place in the circult to another. Rules for applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are also presented. Finally, a case study using a prototype system is described.

关键词： Knowledge Based Systems System Testing Very Large Scale Integration Circuit Testing Design For Testability logic Testing programmable logic arrays Automatic Testing Design Methodology logic Design

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Tailoring the mechanical and thermal properties of polylactic acid-based bionanocomposite films using halloysite nanotubes and polyethylene glycol by solvent casting process

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JOURNAL OF MATERIALS SCIENCE 2019年第12期54卷 8971-8983页

作者： Sharma, Swati Singh, Anshu Anjali Majumdar, Abhijit Butola, Bhupendra Singh Indian Inst Technol Delhi Dept Text Technol New Delhi 110016 India

The inherent brittleness of PLA is a major challenge for its use in various applications. In this study, the effect of incorporation of halloysite nanotube (HNT) and polyethylene glycol (PEG) on mechanical and thermal properties of polylactic acid (PLA) was investigated. Various concentrations of PEG-600 and HNT were used with PLA, and films were prepared by solvent casting method. Mechanical, morphological, and thermal properties of these composite films were investigated to study the effect of PEG and HNT on the properties of PLA. Addition of PEG increased elongation at break, but reduced the tensile strength. However, addition of HNT in PLA/PEG compensated the fall in tensile strength. Addition of 3wt% HNT into PLA blend involving 5wt% PEG increased its elongation at break by 640% and tensile strength by 22%, while no significant change in Young's modulus was observed. Dynamic mechanical thermal analysis (DMTA) showed significant improvement in storage modulus of PLA/PEG/HNT films in the rubbery region. Glass transition temperature decreased for the PEG-plasticized films, while the crystallinity improved as compared to neat PLA. Thermal stability of PLA/PEG/HNT films was higher than those of PLA, PLA/PEG, and PLA/HNT films. The degree of crystallinity obtained using X-ray diffraction analysis showed good agreement with that determined from differential scanning calorimetry (DSC).

关键词： neurotrimin programmable logic arrays Elastic Modulus halloysite Mechanical Differential scanning calorimetry Tensile Strength Films Elongation at break casting process Crystallinity Thermal properties

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A programmable logic ARRAY SUITABLE FOR USE IN DIGITAL SYSTEM-DESIGN LABORATORIES

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IEEE TRANSACTIONS ON EDUCATION 1992年第4期35卷 338-350页

作者： ABE, K OMORI, T NARAOKA, M HITACHI LTD KANAGAWA WORKSRISC DEVKANAGAWA 257JAPAN

A specially designed programmable logic array (PIA) suitable for use in digital system design laboratories for undergraduates is presented. Rewriting the PIA is done just by transfering the new codes;no explicit erasing process is required. The number of product terms allowed to be implemented on the PLA is unlimited. The computation speed of the PLA is reasonably fast (less than 100 ns). The PLA can communicate with a host computer by accepting a variety of commands for writing PIA codes and monitoring input and output values of the PLA. Using software tools developed for the PIA, the student can effectively perform laboratory experiments at various levels. The PIA is viewed on the color display of a personal computer as AND-OR cascaded matrices, each element of which can be activated or inactivated by means of a user-friendly graphics editor. Another software tool permits programming the PLA in a high-level language. The excitation (next-state) and output functions of a controller circuit are naturally described in a simple syntactic construct. Laboratory experiments utilizing the PIA and student responses are also given.

关键词： college student on line data service programmable logic arrays Laboratory Experiments commands

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3D Printing-Assisted Soft Capacitive Inclinometers for Simultaneous Monitoring of Tilt Angles and Directions

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IEEE ACCESS 2022年 10卷 31445-31454页

作者： Baek, Keuntae Bang, Joohyung Lee, Jihun Choi, Minyoung So, Hongyun Hanyang Univ Dept Mech Engn Seoul 04763 South Korea Hanyang Univ Inst Nano Sci & Technol Seoul 04763 South Korea

This study presents capacitive-type inclinometers composed of flexible polymer pillars and dome-shaped roof frames that were manufactured using the three-dimensional (3D) printing method. Polylactic acid (PLA) filaments and acrylonitrile butadiene styrene (ABS) filaments were printed by the fused deposition modeling type 3D printer to fabricate the dome-shaped roof frames and the polymer curing molds, respectively. The operating principle of the inclinometer was to detect the change in capacitance between the helix-shaped electrode coiled around the polymer pillar and the built-in electrode in the roof frame. When the inclinometer was tilted, the polymer pillar was bent, and the physical distance between each electrode was changed with respect to the tilt angle and direction. Therefore, the tilt angles and directions were simultaneously estimated by distinguishing the capacitance and peak capacitance, respectively. The results of the experiments revealed that the inclinometer using the polymer pillar that was electrically connected to a standard weight and the roof frame with a roof angle of 45 degrees exhibited a higher sensitivity (1.391 pF at a tilt angle of 40 degrees) compared to those using roof angles of 90 degrees and 135 degrees. This study supports the use of 3D printing technology for the facile manufacturing of inclinometers that can detect tilt angles and directions simultaneously, which is not achievable with conventional inclinometers.

关键词： Polymers Electrodes Standards Capacitance Copper Temperature measurement programmable logic arrays 3D printing inclinometer capacitive polymer rapid prototyping

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Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2013年第1期12卷 40-50页

作者： Gaillardon, Pierre-Emmanuel Sacchetto, Davide Beneventi, Giovanni Betti Ben Jamaa, M. Haykel Perniola, Luca Clermidy, Fabien O'Connor, Ian De Micheli, Giovanni Ecole Polytech Fed Lausanne Lab Syst Integrat CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Lab MicroElect Syst CH-1015 Lausanne Switzerland Commissariat Energie Atom & Energies Alternat F-38054 Grenoble France Ecole Cent Lyon F-69134 Ecully France Ecole Polytech Montreal PQ H3T 1J4 Canada

Emerging nonvolatile memories (ENVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using ENVMs. We propose an ENVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3x and 33x, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the ENVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack.

关键词： 3-D integration nonvolatile memory oxide memory phase-change memory programmable logic arrays RRAM

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A TECHNIQUE FOR PULL-UP TRANSISTOR FOLDING

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第8期7卷 887-896页

作者： LURSINSAP, C GAJSKI, DD UNIV CALIF IRVINE DEPT INFORMAT & COMP SCIIRVINECA 92717

The authors consider the constraint limiting multiple folding in programmable logic array (PLA) layouts imposed by the layout architecture which positions pull-up transistors on the boundary of the cell and uses another metal layer to connect pull-ups to terms inside the PLA. The general PLA architecture supports only input- and output-port folding by sharing them in either the same column or the same row. Term folding is allowed only with drastic changes in the layout architecture. Folding optimization algorithms, generally, have not considered a pull-up transistor placement as a constraint. A layout architecture is introduced and a technique for pull-up transistor folding based on a weighted-graph model is presented. The architecture supports also both I/O and term foldings. In comparison with other architectures the described architecture allows significant area improvement.< >

关键词： programmable logic arrays Computer architecture Joining processes Uninterruptible power systems Filling Computer science Routing Design automation

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SYNCHRONOUS logic SYNTHESIS - ALGORITHMS FOR CYCLE-TIME MINIMIZATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第1期10卷 63-73页

作者： DEMICHELI, G Comput. Syst. Lab. Stanford Univ. CA USA

A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance is presented. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. Experimental results on benchmark circuits are reported.< >

关键词： Minimization methods Registers Circuit synthesis logic circuits Combinational circuits logic design Network synthesis Integrated circuit synthesis programmable logic arrays Integrated circuit interconnections

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SPACE COMPACTION FOR MULTIPLE-OUTPUT CIRCUITS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第10期7卷 1105-1113页

作者： SERRA, M MUZIO, JC VLSl Design and Test Group Department of Computer Science University of Victoria Victoria BC Canada

A counting signature for multiple-output circuits is introduced. It implements both time compaction and space compaction, such that a single signature is derived for all outputs, using a simple scheme with suitable built-in implementation. It is shown that there exists testability criteria that show deterministically at design time, without full-fault simulation, whether a fault is testable by the signature. The computation of such criteria is straightforward, can be easily incorporated into a CAD system such that the testability results are directly available to the designer. The best current application of such a space-compacted signature is to PLAs (programmable logic arrays) and ROMs (read-only memories), where full testability of all single faults is achieved. Discussion, results, proofs, and examples are presented, including an initial comparison with multiple-input shift registers (MISRs).< >

关键词： Compaction programmable logic arrays Circuit testing Circuit faults logic testing Computational modeling Circuit simulation Design automation System testing Read only memory

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