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Physical Layer Authentication for Industrial Control Based on Convolutional Denoising Autoencoder

IEEE INTERNET OF THINGS JOURNAL 2024年第9期11卷 15633-15641页

作者： Chen, Yanru He, Haoyu Liu, Shengjie Zhang, Yuanyuan Li, Yang Xing, Bin Guo, Bing Chen, Liangyin Sichuan Univ Coll Comp Sci Chengdu 610065 Peoples R China Sichuan Univ Inst Ind Internet Res Chengdu 610065 Peoples R China Inst Southwestern Commun Sci & Technol Secur Commun Lab Chengdu 610041 Peoples R China Ind Big Data Applicat Technol Natl Engn Lab Beijing 100040 Peoples R China

Industrial control systems rely on wireless devices and sensors, necessitating critical security. Physical layer authentication (PLA) is a promising mechanism for device authentication, utilizing its unique spatiotemporal characteristics and channel state randomness, which offers unforgeability and high informatics security with low computational overhead and efficiency in resource-constrained scenarios. However, existing PLA mechanisms face challenges in complex industrial wireless environments, including insufficient accuracy, computational complexity, inadequate noise consideration, and poor performance. To address these challenges, we propose a convolutional denoising autoencoder (CDAE) model that reduces feature dimensions, eliminates noise, and extracts key vectors. The weighted k -nearest neighbor algorithm classifies the extracted vectors for comprehensive authentication in control system networks. Accurate authentication enables efficient detection of malicious attacks. Simulation experiments show that using CDAE-extracted feature vectors achieves over 95% accuracy with only 1% training samples, surpassing channel state information-based authentication by 46.15%, validating the proposed mechanism's effectiveness.

关键词： programmable logic arrays Authentication Feature extraction Wireless communication Security Physical layer Industrial control Denoising autoencoder (DAE) industrial control system industrial wireless network physical layer authentication (PLA)

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EXACT ALGORITHMS FOR OUTPUT ENCODING, STATE ASSIGNMENT, AND 4-LEVEL BOOLEAN MINIMIZATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第1期10卷 13-27页

作者： DEVADAS, S NEWTON, AR UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCI BERKELEY CA 94720 USA

A novel minimization procedure of prime implicant generation and covering that operates on symbolic outputs, rather than binary-valued outputs, is proposed for solving the output encoding problem. An exact solution to this minimization problem is also an exact solution to the encoding problem. While this covering problem is more complex than the classic unate covering problem, a single logic minimization step replaces O(N-factorial) minimizations. The input encoding problem can be exactly solved using multiple-valued Boolean minimization. An exact algorithm is presented for state assignment by generalizing the proposed output encoding approach to the multiple-valued input case. Four-level Boolean minimization entails finding a cascaded pair of two-level logic functions that implement another logic function, such that the sum of the product terms in the two cascaded functions or truth tables is minimum. Four-level Boolean minimization can be formulated as an encoding problem and solved exactly using the proposed algorithms. Preliminary experimental results are presented which indicate that this approach is significantly more efficient than exhaustive search. Computationally efficient heuristic approaches based on the exact algorithms are proposed for output encoding, state assignment, and four-level Boolean minimization.< >

关键词： Encoding Minimization methods Binary codes logic functions Automata programmable logic arrays Boolean functions Cost function Design automation

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Transferable Physical Layer Authentication Based on Time-Varying Patterns Toward Zero Training Deployment for Mobile IIoT Devices

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2024年第5期20卷 7675-7685页

作者： Wang, Qi Pang, Zhibo Liang, Wei Zhang, Jialin Wang, Ke Chinese Acad Sci Inst Robot & Intelligent Mfg Shenyang Inst Automat State Key Lab RobotKey Lab Networked Control Sys Shenyang 110016 Peoples R China ABB Corp Res Dept Automat Technol S-72226 Vasteras Sweden Royal Inst Technol KTH Dept Intelligent Syst S-11428 Stockholm Sweden Chinese Acad Sci Inst Robot & Intelligent Mfg Shenyang 110016 Peoples R China

Physical layer authentication (PLA) is a promising approach to ensure wireless network security. However, existing PLA algorithms require channel state information calibration and model training at each location, which limits the device's mobile ranges. To enable zero training deployment in uncalibrated scenarios, we propose a transferable PLA (TPLA) algorithm. It exploits the channel time-varying patterns as the scenario-independent features to avoid PLA failure in uncalibrated scenarios. To extract transferable time-varying patterns from dynamic industrial mobile environments, a neural network feature extractor is designed by a multibranch parallel architecture with multiscale channel receptive fields. Furthermore, the global and component features are fused by the model-level and decision-level fusion methods to accommodate different transferability and computational cost requirements. In experiments, TPLA achieves below 2.5% authentication error in a new scenario, which proves that TPLA is an important step toward zero training deployment of the PLA algorithm.

关键词： programmable logic arrays Training Feature extraction Authentication Correlation Reliability Mobile handsets Channel state information (CSI) industrial mobile device physical layer authentication (PLA) transferability

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Effect of annealing and orientation on microstructures and mechanical properties of polylactic acid

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POLYMER ENGINEERING AND SCIENCE 2008年第4期48卷 634-641页

作者： Yu, Long Liu, Hongshen Xie, Fengwei Chen, Ling Li, Xiaoxi Commonwealth Sci & Ind Res Org Mat Sci & Engn Sydney NSW Australia S China Univ Technol ERCPSP Ctr Polymers Renewable Resources Guangzhou Guangdong Peoples R China

Two types of polylactic acid (PLA) films (one amorphous and one semi-crystalline) were produced by sheet extrusion. Talc was used as a nucleation agent for the semi-crystalline PLA. The films were annealed above their T-g or were uniaxially orientated in two ways: (1) via a drawing system in front of the extruder and die or (2) via a three-roller stretching system. The slower crystallization rate and lower melting stress of the PLA resulted in amorphous film using the drawing system. Annealing above T-g increased crystallinity and polymer chain relaxation, which resulted in increases in both strength and toughness. Stretching above T-g also produced simultaneous crystallization and chain relaxation, which resulted in increases in both modulus and toughness. Both modulus and tensile strength in the stretching direction were higher than in the crosswise direction. Talc acted not only as a rigid filler to reinforce the PLA, but also as a nucleation agent for the PLA, especially during annealing.

关键词： poly(lactic acid) annealing Mechanical properties Stretch NUCLEAT Films programmable logic arrays

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SUBOPTIMAL SOLUTION FOR PLA MULTIPLE COLUMN FOLDING

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COMPUTER-AIDED DESIGN 1990年第8期22卷 515-526页

作者： LUCCIO, F PINOTTI, MC CNR IST ELABORAZ INFORMAZI-56100 PISAITALY

The paper studies the problem of multiple column folding in the design of compact PLAs of m rows and n columns. A set of theoretical results leads to the construction of a heuristic algorithm which builds the folded P... 详细信息

关键词： multiple column folding heuristic algorithm programmable logic arrays

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Biobased Heat-Triggered Shape-Memory Polymers Based on Polylactide/Epoxidized Natural Rubber Blend System Fabricated via Peroxide-Induced Dynamic Vulcanization: Co-continuous Phase Structure, Shape Memory Behavior, and Interfacial Compatibilization

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INDUSTRIAL & ENGINEERING CHEMISTRY RESEARCH 2015年第35期54卷 8723-8731页

作者： Chen, Yukun Chen, Kunling Wang, Youhong Xu, Chuanhui S China Univ Technol Key Lab Polymer Proc Engn Minist Educ Guangzhou 510640 Guangdong Peoples R China Guangxi Univ Sch Chem & Chem Engn Nanning 530004 Peoples R China

A biobased heat-triggered shape-memory polymer (HSMP) consisting of polylactide (PLA) and epoxidized natural rubber (ENR) was fabricated by peroxide-induced dynamic vulcanization. The cross-linked ENR phase exhibits a continuous net-like structure embedded in the PLA phase, which is different from a conventional plastic/rubber system having the typical "sea-island" morphology in which vulcanized rubber particles were dispersed in plastic matrix. In situ interfacial compatibilization was confirmed by FTIR analysis. The shape-recovery ratios of the PLA/ENR HSMPs were significantly improved over 90%, compared to that (60-70%) of PLA. The shape fixing and memorizing capability of PLA/ENR HSMPs was realized by the glass transition of the PLA phase: cross-linked ENR continuous phase at rubbery state offered strong recovery driving force, improved interface provided effective stress-transferring during shape recovery, and PLA continuous phase served as a "control-switch" for recovery. The biobased PLA/ENR HSMP could serve as a promising alternative to the traditional materials for intelligent biomedical devices.

关键词： programmable logic arrays COMPATIBILISATION traditional materials Sulfidation Glass transition PHASE STRUCTURE rubbers Phase RECYCLING RATE Natural rubber BLENDING SYSTEM

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Processable conductive and mechanically reinforced polylactide/graphene bionanocomposites through interfacial compatibilizer

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POLYMER COMPOSITES 2019年第1期40卷 389-400页

作者： Cai, Chenyang Liu, Linshu Fu, Yu Nanjing Forestry Univ Coll Mat Sci & Engn 159 Longpan Rd Nanjing 210037 Jiangsu Peoples R China ARS USDA Eastern Reg Res Ctr 600 East Mermaid Lane Wyndmoor PA 19038 USA

Novel processable conductive bionanocomposites containing different loadings of graphite nanoplatelets (GNPs) were developed and examined in the experiments. At the same GNPs loadings, the bionanocomposites with interfacial compatibilizer, maleated PLA (ma-PLA), exhibited higher mechanical and thermo-mechanical properties compared to neat PLA and those without ma-PLA. The strong interaction from incorporated interfacial compatibilizer with GNPs was evidenced on the fractured surface. With the micromechanical models, the mechanical properties of the bionanocomposites were evaluated. Also, their thermal and rheological properties were tested and analyzed. An approximately twofold decrease in complex viscosity was achieved for the bionanocomposites with interfacial compatibilizer. For electrical conductivity, at 5-7 wt% GNPs loadings the electrical conduction path was constructed inside the PLA matrix through the formation of the effective three-dimensional conductive networks. It was interestingly noted that above the percolation threshold the increasing GNPs loading did not contribute to the higher but lower AC conductivity. The corresponding mechanisms in AC conductivity were elucidated and discussed. POLYM. COMPOS., 40:389-400, 2019. (c) 2017 Society of Plastics Engineers

关键词： programmable logic arrays Rupture surfaces conductivity rheological properties Mechanical properties

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MCBOOLE - A NEW PROCEDURE FOR EXACT logic MINIMIZATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1986年第1期5卷 229-238页

作者： DAGENAIS, MR AGARWAL, VK RUMIN, NC Department of Electrical Engineering McGill University Montreal QUE Canada

A new logic minimization algorithm is presented. It finds a minimal cover for a multiple-output boolean function expressed as a list of cubes. A directed graph is used to speed up the selection of a minimal cover. Covering cycles are partitioned and branched independently to reduce greatly the branching depth. The resulting minimized list of cubes is guaranteed to be minimal in the sense that no cover with less cubes can exist. The don't care at output is handled properly. This algorithm was implemented in C language under UNIX BSD4.2. An extensive comparison with ESPRESSO IIC shows that the new algorithm is particularly attractive for functions with less than 20 input and 20 output variables.

关键词： Minimization methods Circuits programmable logic arrays Partitioning algorithms Boolean functions logic arrays Input variables Very large scale integration Assembly

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COMBINING MICROCONTROLLER UNITS AND PLDS FOR BEST SYSTEM-DESIGN

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IEEE MICRO 1994年第2期14卷 70-78页

作者： CLAPP, AE HARMAN, TL UNIV HOUSTON CLEAR LAKE 2700 BAY AREA BLVD HOUSTON TX 77058 USA MARQUETTE ELECTR INC DIV MONITORING MILWAUKEE WI USA

Microcontroller timer units and programmable logic devices both can create complex system timing functions. Using the Motorola time processor unit available on the MC68332 and MC68HC16Y1 microcontrollers and PLDs from Altera, we compared the performance and flexibility of these devices in applications that require various timing functions. These investigations show that in certain systems the combination of a microcontroller timer and a PLD provides the most efficient design.

关键词： Microcontrollers Timing programmable logic arrays Macrocell networks logic devices Counting circuits programmable logic devices Control systems logic functions Flip-flops

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OPTIMAL CELL GENERATION FOR DUAL INDEPENDENT LAYOUT STYLES

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第6期10卷 770-782页

作者： CARLSON, BS CHEN, CYR SINGH, U Department of Electrical and Computer Engineering Syracuse University Syracuse NY USA

The need for automatic layout and functional cell generation tools is increasing dramatically due to the fast turnaround time desired in the design of integrated circuits. Many optimization algorithms have been proposed in the literature for layout styles which are dual dependent;that is, the optimization for the layout of the n-transistor network of a CMOS complex gate is dependent on the p-transistor network and vice versa. A two-stage linear-time optimization algorithm is presented for dual independent layout styles in this paper. The first stage is based on a tree representation of the complex gate [8]. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding [13]. The optimization goal is identical to the Euler pathed optimization algorithms presented in [2] and [5]-[9]. The optimization algorithm is applicable to many VLSI layout styles. In this paper, the algorithm is applied to the M3 [4] layout style and examples of generated layouts are shown. Starting from a switching expression, the proposed algorithm always produces an optimal solution in terms of the number of diffusion breaks, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence to traverse this transistor circuit (second stage).

关键词： programmable logic arrays Integrated circuit layout Very large scale integration Switching circuits Design methodology Delay Helium Routing Circuit optimization Automatic logic units

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