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检索条件"主题词=Programmable Logic Arrays"

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Titration Curve Estimation for Adaptive pH Control

Titration Curve Estimation for Adaptive pH Control

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American Control Conference (ACC)

作者： Martin Gullaian John Lane Application Engineering Bailey Controls Company Wickliffe OH USA

High performance pH control requires a good model of the titration curve, whih the described the nonlinear gain of the process. In many applications, the titration curve changes significantly over short periods of time, and some form of online titration curve estimation is essential. Unfortunately, the titration curve is a complex nonlinear function of process composition, and direct estimation of its parameters is difficult. This paper presents an estimation technique which uses as parameters a basis set of entire titration curves. The parameter choice linearizes the estimation problem, and has proven flexible and robust. An adaptive pH controller is described that uses the estimation technique to identify a process model online, and uses the model to provide a gain schedule for a PI controller. Results of pilot plant testing of this controller are presented.

关键词： programmable control Adaptive control Tellurium Hydrogen Robustness programmable logic arrays Testing Job design Biological control systems Water conservation

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A Knowledge based Approach to Malfunction Diagnosis of Discrete Operations Involving programmable logic Controllers

A Knowledge based Approach to Malfunction Diagnosis of Discr...

引用

American Control Conference (ACC)

作者： Douglas R. Myers James F. Davis Charles E. Harley Department of Chemical Engineering Ohio State Uinversity Columbus OH USA Westvaco Bleached Board Division Covington Virginia

Discrete processes controlled by programmable logic controllers involve two distinct diagnostic scenarios: dead state and degrading performance. This paper details a dual-hierarchical expert system approach which performs process diagnosis for both scenarios. Diagnosis of either scenario is classificatory in nature, using one of two specialized Sequential-Functional hierarchies.

关键词： programmable control logic testing logic devices Degradation Chemical industry programmable logic arrays programmable logic devices Industrial control Machinery production industries Switches

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A design planner including a fast predictive floorplanning tool

A design planner including a fast predictive floorplanning t...

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Euro ASIC

作者： E. Chotin A. Mignotte G. Saucier Institut National Polytechnique de Grenoble Grenoble France

The design planner presented in this paper starts from a description of a circuit in terms of interconnected blocks which may be hard blocks (macrocells in a library, generated blocks like RAMs, PLAs) or soft blocks usually generated by synthesis tools. The design planner predicts the cost of a circuit in terms of area, yield and other issues (power, consumption, packaging), according to different technologies. A special attention is given to a fast accurate floorplanning prediction. Experiments on real circuits showed a good prediction accuracy.< >

关键词： Macrocell networks Libraries Application specific integrated circuits CMOS technology Integrated circuit interconnections Power generation programmable logic arrays Circuit synthesis Costs Packaging

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EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions

EXMIN: a simplification algorithm for exclusive-OR-sum-of-pr...

引用

International Symposium on Multiple-Valued logic

作者： T. Sasao Department of Computer Science and Electronic Engineering Kyushu Institute of Technology Iizuka Japan

Minimization of AND-EXOR PLAs (programmable logic arrays) with input decoders corresponds to minimization of the number of products in exclusive-OR sum-of-products (ESOPs) expressions for multiple-valued-input, two-valued-output functions. A simplification algorithm for ESOPs, called EXMIN, is presented. The algorithm is based on an iterative improvement. Seven rules are used to replace one pair of products with another. Many AND-EXOR PLAs for arithmetic circuits are simplified. It is shown that in most cases AND-EXOR PLAs require fewer products than AND-OR PLAs.< >

关键词： programmable logic arrays Computer science Iterative decoding Minimization Iterative algorithms Arithmetic Circuit testing Automatic testing Hardware Algorithm design and analysis

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The hardware and software interface of a programmable logic controller to an industrial grade process control system

The hardware and software interface of a programmable logic ...

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Conference Record of the IEEE Industry Applications Society Annual Meeting (IAS)

作者： A. Hossain M.H. Rashid Technology Department Electrical Engineering Purdue University Calumet Hammond IN USA Engineering Department Purdue University Fort Wayne IN USA

An integrated system that is useful for teaching about the methods of industrial process control, applications of programmable logic controllers, computer aided simulation of process control systems to test designs and advanced animated graphics for data acquisition and control is discussed. The system hardware, including the process control system, programmable logic controller, and microcomputer components, is outlined. The system software, control strategies, and control algorithms are described. The advantages of this integrated system as a teaching tool are reviewed.< >

关键词： Hardware programmable logic arrays programmable logic devices Process control Education programmable control Control systems Computer industry Electrical equipment industry Industrial control

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Synthesis of testable PLAs using adaptive heuristics for efficiency

Synthesis of testable PLAs using adaptive heuristics for eff...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： P. Bose S. Bandyopadhyay D. Dutta Majumder IBM Thomas J. Watson Research Center Yorktown Heights NY USA Electronics and Communication Sciences Unit Indian Statistical Institute Calcutta India Department of Computer Sciences University of Windsor Windsor ONT Canada

The problem of integrating testability issues into the synthesis process of programmable-logic-array (PLA-)based VLSI logic design is investigated. Based on the insight gained from prior work on algorithmic and heuristic test generation for PLAs, a systematic methodology for synthesizing easily testable PLAs from high-level (Boolean) specifications is developed. Experimental results are presented to illustrate how adaptive heuristics aid in reducing the complexity of the synthesis-for-testability problem.< >

关键词： programmable logic arrays logic testing Circuit testing Circuit faults Circuit synthesis Electronic equipment testing logic design System testing Design for testability Automatic testing

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Heuristic minimization of Boolean relations using testing techniques

Heuristic minimization of Boolean relations using testing te...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： A. Ghosh S. Devadas A.R. Newton Department of Electrical Engineering & Computer Sciences University of California Berkeley USA Department of Electrical Engineering & Computer Sciences Massachusetts Institute of Technology Cambridge UK

Minimization of Boolean relations is important from the point of view of synthesis, especially in synthesis for testability. A very fast heuristic procedure for finding an optimal sum-of-products representation for a Boolean relation is described. Starting with a function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a minimal function compatible with the Boolean relation.< >

关键词： programmable logic arrays logic functions logic testing Automata Circuit testing Feeds Cost function Minimization methods Computer science Boolean functions

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Design of repairable and fully testable folded PLAs

Design of repairable and fully testable folded PLAs

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： C.-L. Wey J. Ding Department of Electrical Engineering Michigan State University East Lansing MI USA

The yield of ICs is crucial to the commercial success of their manufacture. One practical solution to the low yield problem is the use of fault-tolerant design. A fault diagnosable and repairable PLA design has been proposed to detect, locate, and repair faults, and has led to a significant yield improvement. An alternated defect-tolerant design of PLAs with folding technique is presented to further improve chip yield. The proposed design achieves full diagnosability of stuck-at, bridging, and crosspoint faults during the manufacturing process, and provides full testability after the chip is packaged.< >

关键词： Testing programmable logic arrays Circuit faults Manufacturing processes Shift registers Fault tolerance Probes Routing Switches Fault detection

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HDL driven chip layout within the FHDL design framework

HDL driven chip layout within the FHDL design framework

引用

IEEE Southeastcon

作者： C.D. Morency P.M. Maurer Z. Wang Department of Computer Science and Engineering University of South Florida Tampa FL USA

Techniques of automatically generating layout from Florida Hardware Design Language (FHDL) specifications are presented. These techniques allow for the automated layout of read-only memories (ROMs) and programmable logic arrays (PLAs), and they allow for the user-assisted automatic layout of standard-cell blocks. Adaptations of the FHDL and its framework to permit layout synthesis are presented. Cell generation is discussed. Adapting the simulation framework and primitive simulation modelling are discussed.< >

关键词： Hardware design languages programmable logic arrays Integrated circuit synthesis Circuit synthesis Read only memory Packaging Computer languages Routing Central Processing Unit Delay

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An algorithm for the reconfiguration of I/O buffers

An algorithm for the reconfiguration of I/O buffers

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： J. Narasimhan K. Nakajima Electrical Engineering Department and Systems Research Center University of Maryland College Park MD USA Maryland Univ. College Park MD USA

A problem of reconfiguration of I/O buffers located on the periphery of a programmable gate array is considered. This problem is treated as a problem of shifting pebbles on a cycle. An O(mn) time algorithm is presented, where n and m are the numbers of all I/O buffers and used defective I/O buffers, respectively. A few lemmas are established that aid in the development of the algorithm.< >

关键词： programmable logic arrays Electronics packaging Circuit testing Circuit faults Costs Clocks

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