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检索条件"主题词=Programmable Logic Arrays"

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A VLSI floorplanner based on 'balloon' expansion

A VLSI floorplanner based on 'balloon' expansion

引用

European Design Automation Conference

作者： N. Yonezawa N. Nishiguchi A. Etani F. Tsukuda R. Hashishita NEC Corporation Limited Kanagawa Japan

A novel floorplanning method is presented that models blocks as rectangular 'balloons', which are gradually expanded to determine their shapes and placement. Unlike the existing approaches, which assume the floorplan to be a slicing structure or which never handle fixed-shaped blocks, this method can handle fixed-shaped blocks as well as variable-shaped blocks on a general (non-slicing) layout structure. Experimental results show that the proposed method works effectively and gives an accurate estimate of chip area with only 3 to 6 percent difference from final layout, especially when the fixed- and variable-shaped blocks are mixed.< >

关键词： Very large scale integration Shape Routing National electric code Chip scale packaging programmable logic arrays Reactive power Iterative algorithms

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The 68040 integer and floating-point units

The 68040 integer and floating-point units

引用

IEEE Compcon

作者： B. Ledbetter R. McGarity E. Quintana R. Reininger Motorola Inc. Austin TX USA

The integer, floating-point, and on-chip memory subsystems of the Motorola 68040 microprocessor operate in parallel to achieve four times the performance of a 68020 microprocessor and ten times the performance of a 68882 floating-point coprocessor. The integer and floating-point units are described in terms of their performance, internal architecture, and methods used to obtain this performance. The 68040 integer unit (IU) is optimized to execute the most common instructions in a single cycle while maintaining user code compatibly with the 68000 family. To increase performance, the 68040 reduces both the number of arithmetic logic unit (ALU) cycles per instruction (CPI) and the ALU cycle time. The 68040 has a six-stage pipe consisting of an instruction prefetch stage, a program counter calculation and decode stage, an effective address calculation stage for operands, a data execute stage, and a write-back stage. The 68040 floating-point unit (FPU) conforms to the IEEE 754 floating-point standard via a software envelope.< >

关键词： Decoding Microprocessors Clocks Pipeline processing Coprocessors programmable logic arrays Instruction sets Frequency Memory management Operating systems

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CGASC-a silicon compiler for the CMOS gate array

CGASC-a silicon compiler for the CMOS gate array

引用

International Phoenix Conference on Computers and Communications (IPCCC)

作者： J. Hu Department of Electrical Engineering Tulane University New Orleans LA USA

Summary form only given. A new silicon compiler for the CMOS gate array named CGASC, for automating the complex task of chip designing, is presented. CGASC accepts the hardware description language AHPL (a hardware programming language) or VHDL (VHSIC hardware description language) as input and compiles the described circuit into the CMOS gate array device. The automation of the compiler includes the chip size estimation, the floor planning, and placement, the channel ordering and routing, and the layout generation. Active modules of CGASC include a logic optimizer, a modular circuit partitioner, a hierarchical floor planner, a pseudocontinuous cell allocator, a global router, and a detailed router. The design goal of CGASC was to synthesize a complex digital circuit from behavioral-level input to mask-level output with as little manual intervention as possible. The development of CGASC proves the feasibility of using hardware description languages as the input media of hardware compilers. During applications, CGASC estimates chip size and allows users to select the most appropriate chip based on the basis of the availability of IC markets. Online interactive routing is also available to facilitate the zoom-in/out of a critical routing area and the modification of routing configuration.< >

关键词： Silicon compiler Routing Hardware design languages Computer languages Very high speed integrated circuits programmable logic arrays Automation CMOS logic circuits logic devices logic circuits

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VLSI implementation of an entropy coder and decoder for advanced TV applications

VLSI implementation of an entropy coder and decoder for adva...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Lei M.-T. Sun K. Ramachandran S. Palaniraj Bell Communications Research Inc. Red Bank NJ USA

Experimental prototype high-speed entropy coder and decoder chips with parallel architectures are discussed. Two coding techniques, run-length coding and variable-length coding, are implemented in these two chips. Designed in a 1.2- mu m double-metal CMOS technology, the die-size of each chip is about 5 mm*5 mm. Each chip contains about 35 K transistors. Based on the simulation of critical parts, they are expected to meet a speed objective of 52 MHz with margin.< >

关键词： Very large scale integration Entropy Decoding HDTV Prototypes programmable logic arrays Sampling methods CMOS technology TV Video compression

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Using Operational Calculus to Obtain Transient Response Estimates in Linear Uncertain Feedback Systems

Using Operational Calculus to Obtain Transient Response Esti...

引用

American Control Conference (ACC)

作者： Yossi Chait Neil F. Lacey C.R. MacCluer Department of Mechanical Engineering University of Massachusetts USA Department of Mathematics Michigan State University USA

A new methodology is presented for deriving transient response estimates for a large class of uncertain linear feedback SISO systems, including unstable distributed parameter systems. It is shown that, using operational calculus, estimates exist and can be computed even in cases where a certain error norm is greater than unity. Several simple examples illustrate the application of the method.

关键词： Calculus Transient response Feedback Robustness Tellurium Chromium Table lookup programmable logic arrays Control systems Uncertainty

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BIST PLAs, pass or fail-a case study

BIST PLAs, pass or fail-a case study

引用

Design Automation Conference

作者： S.J. Upadhyaya J.A. Thodiyil Department of Electrical and Computer Engineering State University of New York University at Buffalo Buffalo NY USA

Numerous built-in self-testing (BIST) designs exist for the testing of programmable logic arrays (PLA), but their practical usefulness has not been studied. Several BIST designs were implemented and compared using a common methodology of implementation. A yield analysis is performed to characterize the yield degradation due to the BIST design methodology. Preliminary findings of this work are that the BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.< >

关键词： Built-in self-test programmable logic arrays Computer aided software engineering logic testing Automatic testing logic design Neodymium Performance analysis Degradation Vehicles

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Performance-driven layout of CMOS VLSI circuits

Performance-driven layout of CMOS VLSI circuits

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S.M. Kang Department of Electrical and Computer Engineering Coordinated Science Laboratory and Beckman Institute University of Illinois Urbana-Champaign Urbana IL USA

As design rules get scaled down to submicron dimensions, physical CAD tools need to be much more performance-driven as opposed to purely geometry-driven. For instance, to help prevent timing bottlenecks, it is necessary to consider timing-critical nets during circuit partitioning, placement, and routing phases. Long parallel lines can cause crosstalk problems; therefore, it is prudent to limit the length of parallel runners, especially in high-speed circuit layout. The issues are even more complex in active circuit layout. For sensitive analog circuits or clock distribution circuits, various symmetry constraints need to be met. Recent developments in performance-driven layout techniques are reviewed, and these newly emerging issues are discussed.< >

关键词： Very large scale integration Circuits programmable logic arrays Read only memory Design engineering Chip scale packaging Parameter estimation Productivity CMOS technology Design automation

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The effect of switch box flexibility on routability of field programmable gate arrays

The effect of switch box flexibility on routability of field...

引用

Custom Integrated Circuits Conference (CICC)

作者： J. Rose S. Brown Department of Electrical Engineering University of Toronto ONT Canada

The relationship between the routability of a field programmable gate array (FPGA) and the flexibility of its interconnection structures is explored. A set of industrial circuits are implemented as FPGAs in a range of routing structures with varying flexibility. Experiments indicate that high flexibility is essential for the connection box that joint the logic blocks to the routing channel, but a relatively low flexibility is sufficient for switch boxes at the junction of horizontal and vertical channels.< >

关键词： Switches Field programmable gate arrays Routing Integrated circuit interconnections programmable logic arrays logic devices Switching circuits Flexible printed circuits Design automation Industrial relations

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Interchanging terminals for improved channel routing

Interchanging terminals for improved channel routing

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： I.G. Tollis S.G. Tragoudas Department of Computer Science University of Texas Dallas Richardson TX USA

The problem of interchanging the terminals on the cells at the sides of a channel in order to obtain new channels that can be routed more efficiently is considered. A linear-time algorithm that detects whether there exists an interchange of the terminals that produces a river routable problem is given, and O(n/sup 2/) algorithm that finds a terminal permutation that guarantees that the density of the channel routing problem is minimal over all possible permutations is presented.< >

关键词： Routing Rivers Very large scale integration programmable logic arrays Computer science Circuits logic design programmable logic devices Read only memory Geometry

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Wafer scale integration (WSI) of programmable gate arrays (PGA's)

Wafer scale integration (WSI) of programmable gate arrays (P...

引用

International Conference on Wafer Scale Integration

作者： J.F. McDonald S. Dabral R. Philhower M.E. Russinovich Center for Integrated Electronics Rensselaer Polytechnic Institute Troy NY USA

Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as programmable Gate Array (PGA), which is also known as a logic Component Array (LCA).< >

关键词： Wafer scale integration Electronics packaging Integrated circuit interconnections Wiring programmable logic arrays Delay Circuit faults Fabrication Integrated circuit manufacture Testing

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